Early evaluation for performance enhancement in phased logic

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 24, Issue 4, 2005, Pages 532-550

  Reese, Robert B ^a   Traver, Cherrice ^c   Thornton, Mitchell Aaron ^b   Hemmendinger, David ^c  

^a MISSISSIPPI STATE UNIVERSITY   (United States)

^b Southern Methodist University   (United States)

^c UNION COLLEGE   (United States)

Author keywords

Asynchronous logic circuits; Early evaluation; Level encoded dual rail; Marked graphs; Phased logic

Indexed keywords

ALGORITHMS; AUTOMATION; BENCHMARKING; COMPUTER SIMULATION; DIGITAL ARITHMETIC; FEEDBACK; GRAPH THEORY; LOGIC DESIGN;

ASYNCHRONOUS LOGIC CIRCUITS; EARLY EVALUATION; LEVEL-ENCODED DUAL-RAIL; MARKED GRAPHS; PHASED LOGIC;

LOGIC CIRCUITS;

EID: 16444362672     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.844084     Document Type: Article

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