Resource allocation and binding approach for low leakage power

Proceedings of the IEEE International Conference on VLSI Design

Volumn 2003-January, Issue , 2003, Pages 297-302

  Gopalakrishnan, C ^a   Katkoori, S ^a  

^a University of South Florida   (United States)

Author keywords

Circuits; CMOS technology; High level synthesis; Leakage current; Libraries; Minimization; Performance loss; Resource management; Sleep; Very large scale integration

Indexed keywords

CMOS INTEGRATED CIRCUITS; DESIGN; ECONOMIC AND SOCIAL EFFECTS; EMBEDDED SOFTWARE; EMBEDDED SYSTEMS; GATES (TRANSISTOR); HIGH LEVEL SYNTHESIS; LIBRARIES; NETWORKS (CIRCUITS); OPTIMIZATION; RESOURCE ALLOCATION; SLEEP RESEARCH; SYSTEMS ANALYSIS; TRANSISTORS; VLSI CIRCUITS;

CMOS TECHNOLOGY; LEAKAGE POWER REDUCTION; MULTI-THRESHOLD CMOS; PERFORMANCE LOSS; PERFORMANCE PENALTIES; PERFORMANCE RECOVERY; RESOURCE MANAGEMENT; SLEEP;

LEAKAGE CURRENTS;

EID: 84941358756     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICVD.2003.1183153     Document Type: Conference Paper

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