Power characterization of digital filters implemented on FPGA

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2002, Pages

  Cardarilli, Gian Carlo ^a   Del Re, Andrea ^a   Nannarelli, Alberto ^a   Re, Marco ^a  

^a UNIVERSITY OF ROME TOR VERGATA   (Italy)

Author keywords

[No Author keywords available]

Indexed keywords

ABSORPTION; COMPUTER SIMULATION; CONFORMAL MAPPING; FIELD PROGRAMMABLE GATE ARRAYS; MATHEMATICAL MODELS;

POWER CHARACTERIZATION; RESIDUE NUMBER SYSTEM;

FIR FILTERS;

EID: 0036288069     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Trade-offs between residue number system and traditional FIR filters
2. VLSI implementation of very high-order FIR filters
3. A high-speed realization of a residue to binary number system converter
4. FPGA implementation of RNS to binary signed conversion architecture
5. Implementation of digital filters in carry-save residue number system