The care and feeding of your statistical static timer

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 138-139

  Nassif, Sani R ^a   Boning, Duane ^b   Hakim, Nagib ^c  

^a IBM   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^c INTEL CORPORATION   (United States)

Author keywords

Integrated Circuit; Variability

Indexed keywords

CIRCUIT FABRICATION; DESIGN FOR MANUFACTURABILITY (DFM); STATIC TIMING ANALYSIS (STA); WAFER-LEVEL PHENOMENON;

COMPUTER AIDED DESIGN; COMPUTER HARDWARE; COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; DISCRETE TIME CONTROL SYSTEMS; ELECTROMIGRATION; MATHEMATICAL MODELS; MOSFET DEVICES; ROBUSTNESS (CONTROL SYSTEMS); SPURIOUS SIGNAL NOISE; THERMAL EFFECTS; TIME SERIES ANALYSIS; WSI CIRCUITS;

TIMING CIRCUITS;

EID: 16244391457     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. S. Nassif "Modeling and Analysis of Manufacturing Variations," Proceedings of CICC, 2001.
2. C. Viswesvariah "Statistical Timing of Digital Integrated Circuits," Proceedings of ISSCC, 2004.
3. L. Liebmann "Resolution Enhancement Techniques in Optical Lithography, It's not just a Mask Problem" Proceedings of ISPD, 2003.
4. A. Bhavnagarwala and B. Austin and A. Kapoor and J. Meindl, "CMOS system-on-a-chip voltage scaling beyond 50nm" Proceedings of GLVLSI, 2000.
5. V. Mehrotra and S. Nassif and D. Boning and J. Chung, "Modeling the Effects of Manufacturing Variations on High-Speed Microprocessor Interconnect Performance", Proceedings of IEDM, 1998.
6. B. Stine and D. Boning and J. Chung "Analysis and Decomposition of Spatial Variation in Integrated Circuit Processes and Devices", IEEE Trans. Semiconductor Manufacturing, Feb 1997.
7. M. Orshansky and C. Spanos and C. Hu "Circuit performance variability decomposition" Proceedings of IWSM, 1999.
8. K. Bowman and T. Xinghai and J. Eble and J. Menldl "Impact of extrinsic and intrinsic parameter fluctuations on CMOS circuit" IEEE Journal of Solid State Circuit, Aug 2000.
9. M. Orshansky and L. Milor and P. Chen and K. Keutzer and C. Hu "Impact of Systematic Spatial Intra-Chip Gate Length Variability on Performance of High-Speed Digital Circuits" Proceedings of ICCAD, 2000.
10. R. Ahmadi and F. Najm "Timing Analysis in Presence of Power Supply and Ground Voltage Variations" Proceedings of ICCAD, 2004.
11. R. Arunachalam and K. Rajagopal and L. Pileggi "TACO: Timing Analysis with Coupling" Proceedings of DAC, 2000.
12. D. Boning and J. Panganiban and K. Gonzalez-Valentin and S. Nassif and C. McDowell and A. Gattiker and F. Liu "Test structures for delay variability", Proceedings of TAU, 2002.