CMOS system-on-a-chip voltage scaling beyond 50 nm

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2000, Pages 7-12

  Bhavnagarwala, Azeez J ^a   Austin, Blanca ^a   Kapoor, Ashok ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CELLULAR ARRAYS; INTEGRATED CIRCUIT LAYOUT; LEAKAGE CURRENTS; MOSFET DEVICES; SEMICONDUCTOR DEVICE MODELS; THRESHOLD VOLTAGE;

MACROCELL;

CMOS INTEGRATED CIRCUITS;

EID: 0033726788     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/330855.332574     Document Type: Conference Paper

References (19)