SCOPUS 정보 검색 플랫폼

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2002, Pages 356-362

Data cache design considerations for the Itanium® processor

(4) Lyon, Terry a Delano, Eric a McNairy, Cameron a Mulla, Dean a

a HEWLETT PACKARD COMPANY (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CACHE MEMORY; COMPUTER SIMULATION; DIGITAL ARITHMETIC; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; RESOURCE ALLOCATION; RESPONSE TIME (COMPUTER SYSTEMS); STORAGE ALLOCATION (COMPUTER);

DATA CACHE DESIGN; EXPLICITLY PARALLEL INSTRUCTION COMPUTING; ITANIUM PROCESSOR FAMILY;

COMPUTER ARCHITECTURE;

EID: 0036403199 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper

Times cited : (21)

References (9)

1
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- Itanium processor microarchitecture
- Sept-Oct
- Harsh Sharangpani, et al., "Itanium Processor Microarchitecture," IEEE Micro, Sept-Oct 2000, pp. 24-43.
- (2000) IEEE Micro , pp. 24-43
- Sharangpani, H.¹

2
- 0004003926
- Itanium processor microarchitecture reference for software optimization
- August; Order Number 245473, Intel Corp
- Harsh Sharangpani, et al., "Itanium Processor Microarchitecture Reference for Software Optimization", August 2000, Order Number 245473, Intel Corp or http://developer.intel.com/design/ia64/downloads/245474.htm.
- (2000)
- Sharangpani, H.¹

3
- 0033892359
- EPIC: Explicitly parallel instruction computing
- Feb
- M.S. Schlansker and B. R. Rau, "EPIC: Explicitly Parallel Instruction Computing," Computer, Feb 2000, pp. 37-45.
- (2000) Computer , pp. 37-45
- Schlansker, M.S.¹ Rau, B.R.²

4
- 0004027118
- Order # 245317-9; Intel Corp.
- M.S. Schlansker and B. R. Rau, "Intel IA-64 Architecture Software Developer's Manual", Order # 245317-9 (volume 1-4), Intel Corp.
- Intel IA-64 Architecture Software Developer's Manual , vol.1-4
- Schlansker, M.S.¹ Rau, B.R.²

5
- 0036117607
- The 16kB single-cycle read access cache on a next generation 64b itanium microprocessor
- Feb.
- D. Bradley, P. Mahoney, and B. Stackhouse, "The 16kB Single-Cycle Read Access Cache on a Next Generation 64b Itanium Microprocessor", 2002 IEEE International Sold-State Circuits Conference Digest of Technical Papers, pages 110-111, Feb., 2002.
- (2002) 2002 IEEE International Sold-State Circuits Conference Digest of Technical Papers , pp. 110-111
- Bradley, D.¹ Mahoney, P.² Stackhouse, B.³

6
- 85013864971
- Contrasting characteristics and cache performance of technical and Multi-user commercial workloads
- Oct.
- A. Maynard, C. Donnelly, and B. Olszewski, "Contrasting Characteristics and Cache Performance of Technical and Multi-User Commercial Workloads", Proc. Intl. Conf. Arch. Support for Prog. Lang. And Op. Sys., pages 145-156, Oct. 1994.
- (1994) Proc. Intl. Conf. Arch. Support for Prog. Lang. and Op. Sys. , pp. 145-156
- Maynard, A.¹ Donnelly, C.² Olszewski, B.³

7
- 0033314238
- Impact of chip-level integrations on performance of OLTP workloads
- L. Barroso et al., "Impact of chip-level integrations on performance of OLTP workloads", Sixth Intl. Sym. On High-Performance Computer Architecture, pages 3-14.
- Sixth Intl. Sym. on High-Performance Computer Architecture , pp. 3-14
- Barroso, L.¹

8
- 0035390811
- A high-bandwidth memory pipeline for wide issue processors
- July
- S. Cho, P. Yew, G. Lee, "A high-bandwidth memory pipeline for wide issue processors", IEEE Transactions on Computers, Vol. 50, Issue 7, July 2001, pages 709-723.
- (2001) IEEE Transactions on Computers , vol.50 , Issue.7 , pp. 709-723
- Cho, S.¹ Yew, P.² Lee, G.³

9
- 0010973922
- http://www.math.utah:8080/pub/benchmarks/local/index.html

* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.