-
4
-
-
0034259185
-
Crosstalk driven interconnect optimization by simultaneous gate and wire sizing
-
Sept.
-
I. H. R. Jiang, Y. W. Chang, and J. Y. Jou, "Crosstalk driven interconnect optimization by simultaneous gate and wire sizing," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 999-1010, Sept. 2000.
-
(2000)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 999-1010
-
-
Jiang, I.H.R.1
Chang, Y.W.2
Jou, J.Y.3
-
6
-
-
0031619501
-
Buffer insertion for noise and delay optimization
-
C. J. Alpert, A. Devgan, and S. T. Quay, "Buffer insertion for noise and delay optimization," in Proc. Design Automation Conf., pp. 362-367, 1998.
-
(1998)
Proc. Design Automation Conf.
, pp. 362-367
-
-
Alpert, C.J.1
Devgan, A.2
Quay, S.T.3
-
7
-
-
0032690813
-
Noise-aware repeater insertion and wire sizing for on-chp interconnect using hierarchical moment-matching
-
June
-
C.-P. Chen and N. Menezes, "Noise-aware repeater insertion and wire sizing for on-chp interconnect using hierarchical moment-matching," in Proc. Design Automation Conf., pp. 502-506, June 1999.
-
(1999)
Proc. Design Automation Conf.
, pp. 502-506
-
-
Chen, C.-P.1
Menezes, N.2
-
9
-
-
0033697586
-
Can recursive bisection alone produce routable, placements?
-
A. E. Caldwell, A. B. Kahng, and I. L.Markov, "Can recursive bisection alone produce routable, placements?" in Proc. Design Automation Conf., pp. 477-482, 2000.
-
(2000)
Proc. Design Automation Conf.
, pp. 477-482
-
-
Caldwell, A.E.1
Kahng, A.B.2
Markov, I.L.3
-
10
-
-
0037387687
-
Routability-driven white space allocation for fixed-die standard-cell placement
-
Apr.
-
X. Yang, B.-K. Choi, and M. Sarrafzadeh, "Routability-driven white space allocation for fixed-die standard-cell placement," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 410-419, Apr. 2003.
-
(2003)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 410-419
-
-
Yang, X.1
Choi, B.-K.2
Sarrafzadeh, M.3
-
11
-
-
0037343668
-
Early probabilistic noise estimation for capacitively coupled interconnects
-
Mar.
-
M. R. Becer, D. Blaauw, R. Panda, and I. N. Hajj, "Early probabilistic noise estimation for capacitively coupled interconnects," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 337-345, Mar. 2003.
-
(2003)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 337-345
-
-
Becer, M.R.1
Blaauw, D.2
Panda, R.3
Hajj, I.N.4
-
12
-
-
0032139262
-
Prima: Passive reduced-order interconnect macromodeling algorithm
-
Aug.
-
A. Odabasioglu, M. Celik, and L. T. Pileggi, "Prima: passive reduced-order interconnect macromodeling algorithm," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 645-653, Aug. 1998.
-
(1998)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 645-653
-
-
Odabasioglu, A.1
Celik, M.2
Pileggi, L.T.3
-
13
-
-
0346148463
-
On whitespace and stability in mixed-size placement and physical synthesis
-
S. N. Adya, I. Markov, and P. Villarrubia, "On whitespace and stability in mixed-size placement and physical synthesis," in Proc. Int. Conf. on Computer Aided Design, pp. 311-318, 2003.
-
(2003)
Proc. Int. Conf. on Computer Aided Design
, pp. 311-318
-
-
Adya, S.N.1
Markov, I.2
Villarrubia, P.3
-
14
-
-
0028745111
-
A weighted steiner tree-based global router with simultaneous length and density minimization
-
Dec.
-
C. Chiang, C. K. Wong, and M. Sarrafzadeh, "A weighted steiner tree-based global router with simultaneous length and density minimization," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1461-1469, Dec. 1994.
-
(1994)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 1461-1469
-
-
Chiang, C.1
Wong, C.K.2
Sarrafzadeh, M.3
-
16
-
-
0030086676
-
A global router with a theoretical bound on the optimal solution
-
Feb.
-
R. C. C. IV, J. Li, and C. K. Cheng, "A global router with a theoretical bound on the optimal solution," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 208-216, Feb. 1996.
-
(1996)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 208-216
-
-
C. IV, R.C.1
Li, J.2
Cheng, C.K.3
-
17
-
-
0027222295
-
Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs
-
T. Sakurai, "Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs," IEEE Trans. on Electron Devices, vol. 40, pp. 118-124, 1993.
-
(1993)
IEEE Trans. on Electron Devices
, vol.40
, pp. 118-124
-
-
Sakurai, T.1
-
20
-
-
0031336414
-
Efficient coupled noise estimation for on-chip interconnects
-
Nov.
-
A. Devgan, "Efficient coupled noise estimation for on-chip interconnects," in Proc. Int. Conf. on Computer Aided Design, pp. 147-153, Nov. 1997.
-
(1997)
Proc. Int. Conf. on Computer Aided Design
, pp. 147-153
-
-
Devgan, A.1
-
21
-
-
0033320052
-
Crosstalk in VLSI interconnections
-
A. Vittal, L. Chen, M. Marek-Sadowska, K.-P. Wang, and S. Yang, "Crosstalk in VLSI interconnections," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 18, no. 2, pp. 1817-24, 1999.
-
(1999)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, vol.18
, Issue.2
, pp. 1817-1824
-
-
Vittal, A.1
Chen, L.2
Marek-Sadowska, M.3
Wang, K.-P.4
Yang, S.5
-
22
-
-
85030259511
-
Noise and delay uncertainty studies for coupled re interconnects
-
A. B. Kahng, S. Muddu, and D. Vidhani, "Noise and delay uncertainty studies for coupled re interconnects," in IEEE International ASIC/SOC Conference, pp. 3-8, 1999.
-
(1999)
IEEE International ASIC/SOC Conference
, pp. 3-8
-
-
Kahng, A.B.1
Muddu, S.2
Vidhani, D.3
-
23
-
-
0142118141
-
Effective free space management for cut-based placement via analytical constraint generation
-
Oct.
-
C. J. Alpert, G.-J. Nam, and P. G. Villarrubia, "Effective free space management for cut-based placement via analytical constraint generation," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, pp. 1343-1353, Oct. 2003.
-
(2003)
IEEE Trans. on Computer-aided Design of Integrated Circuits and Systems
, pp. 1343-1353
-
-
Alpert, C.J.1
Nam, G.-J.2
Villarrubia, P.G.3
-
25
-
-
0034477836
-
Dragon2000: Standard-cell placement tool for large industry circuits
-
M. Wang, X. Yang, and M. Sarrafzadeh, "Dragon2000: Standard-cell placement tool for large industry circuits," in Proc. Int. Conf. on Computer Aided Design, pp. 260-263, 2000.
-
(2000)
Proc. Int. Conf. on Computer Aided Design
, pp. 260-263
-
-
Wang, M.1
Yang, X.2
Sarrafzadeh, M.3
-
26
-
-
0024890267
-
IBM RISC chip design methodology
-
P. Villarrubia, G. Nusbaum, R. Masleid, and P. T. Patel, "IBM RISC chip design methodology," in Proc. IEEE Int. Conf on Computer Design, pp. 143-147, 1989.
-
(1989)
Proc. IEEE Int. Conf on Computer Design
, pp. 143-147
-
-
Villarrubia, P.1
Nusbaum, G.2
Masleid, R.3
Patel, P.T.4
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