Timing analysis considering spatial power/ground level variation

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2004, Pages 814-820

  Hashimoto, Masanori ^a   Yamaguchi, Junji ^a   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLITUDE; EQUALIZATION; GATE DELAY; OUTPUT LOAD;

COMPUTER SIMULATION; ELECTRIC LOADS; ERROR ANALYSIS; MATHEMATICAL MODELS; PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE; TECHNOLOGY;

LOGIC CIRCUITS;

EID: 16244369101     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2004.1382687     Document Type: Conference Paper

References (13)

1. J.-J. Liou, A. Krstic, Y.-M. Jiang and K.-T. Cheng, "Path Selection and Pattern Generation for Dynamic Timing Analysis Considering Power Supply Noise Effects," Proc. ICCAD, pp. 493-496, 2000.
2. G. Bai, S. Bobba and I. N. Hajj, "Static Timing Analysis Includeing Power Supply Noise Effect on Propagation Delay in VLSI Circuits," Proc. DAC, 2001.
3. L. H. Chen, M. Marek-Sadowska and F. Brewer, "Coping with Buffer Delay Change due to Power and Ground Noise," Proc. DAC, pp. 860-865, 2002.
4. S. Pant, D. Blaauw, V. Zolotov, S. Sundareswaran and R. Panda, "Vectorless Analysis of Supply Noise Induced Delay Variation," Proc. ICCAD, pp.184-191, 2003.
5. R. Ahmadi and F. N. Najm, "Timing Analysis in Presence of Power Supply and Ground Voltage Variations," Proc. ICCAD, pp.176-183, 2003.
6. M. Saint-Laurent and M. Swaminathan, "Impact of Power-Supply Noise on Timing in High-Frequency Microprocessors," IEEE Trans. on Advanced Packaging, Vol. 27, No. 1, Febrary 2004.
7. T. Sakurai and A. R. Newton, "Alpha-Power Law MOS-FET Model and Its Application to CMOS Inverter Delay and Other Formulas," IEEE Journal of Solid-State Circuits, Vol.25, No.2, pp.584-594, Apr. 1990. n
8. T. Sakurai and A. R. Newton, "Delay Analysis of Series-Connected MOSFET Circuits" IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, pp. 122-131, Feb 1991.
9. F. Chang, C. Chen and Prasad Subramaniam, "An Accurate and Efficient Gate Level Delay Calculator for MOS Circuits," Proc. DAC, pp. 282-287, 1988.
10. W. G. Cochran and G. M. Cox, "Experimental Designs," John Wiley & Sons, Inc., 2nd edition, 1957.
11. V. Gerousis, "Design and Modeling Challenges for 90 nm and 50nm," Proc. CICC, pp.353-360, 2003.
12. P. R. O'Brien and T. L. Savarino, "Modeling the Driving-Point Characteristic of Resistive Interconnect for Accurate Delay Estimation," Proc. ICCAD, pp. 512-515, 1989.
13. C. Cheng, J. Lillis, S. Lin and N. H. Chang, "Interconnect Analysis and Synthesis," A Wiley Interscience Publication, 2000.