Timing Analysis in Presence of Power Supply and Ground Voltage Variations

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2003, Pages 176-183

  Ahmadi, Rubil ^a   Najm, Farid N ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DELAY CIRCUITS; ELECTRIC LOADS; INTERCONNECTION NETWORKS; LOGIC GATES; RANDOM NUMBER GENERATION; SIGNAL THEORY; VOLTAGE MEASUREMENT; WAVEFORM ANALYSIS;

DEEP SUB-MICRON (DSM) TECHNOLOGY; STAIC TIMING ANALYSIS (STA); SUPPLY VOLTAGE;

ELECTRIC POWER SUPPLIES TO APPARATUS;

EID: 0348040157     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/iccad.2003.159687     Document Type: Conference Paper

References (7)

1. D. Blaauw, V. Zolotov, and S. Sundareswaran. Slope propagation in static timing analysis. IEEE Transactions on Computer-Aided Design, 21(10):1180-1195, Oct. 2002.
2. N. Hedenstierna and K. O. Jeppson. CMOS circuit speed and buffer optimization. IEEE Trans. on Computer-Aided Design, 6(2):270-281, March 1987.
3. R. B. Hitchcock, S. G. L. Smith, and D. D. Cheng. Timing analysis of computer hardware. IBM Journal of Research and Development, 26(1):100-105, Jan. 1982.
4. T. I. Kirkpatrick and N. R. Clark. PERT as an aid to logic design. IBM Journal of Research and Development, 10(2):135-141, March 1966.
5. C. L. Ratzlaff and L. T. Pillage. RICE: rapid interconnect circuit evaluation using AWE. IEEE Trans. on Computer-Aided Design, 13(6):763-776, June 1994.
6. J. Rubenstein, P. Penfield, Jr., and M. A. Horowitz. Signal delay in RC tree networks. IEEE Transactions on Computer-Aided Design, CAD-2(3):202-211, July 1983.
7. B. Widrow. Adaptive signal processing. Prentice-Hall, 1st edition, 1985.