SPIN-SIM: Logic and fault simulation for speed-independent circuits

Proceedings - International Test Conference

Volumn , Issue , 2004, Pages 597-606

  Shi, Feng ^a   Makris, Yiorgos ^a  

^a Yale University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DESIGN FOR TESTABILITY; ELECTRIC FAULT CURRENTS; GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; LOGIC DEVICES; VLSI CIRCUITS;

COMMERCIAL TESTERS; FAULT COVERAGE; FAULT SIMULATION; SIGNAL TRANSITIONS;

LOGIC CIRCUITS;

EID: 16244364183     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)

1. S. Baneijee, S. T. Chakradhar, and R. K. Roy, "Synchronous test generation model for asynchronous circuits," in Proceedings of the 9th International Conference on VLSI Design, 1996, pp. 178-85.
2. M. A. Breuer, "The effects of races, delays, and delay faults on test generation," IEEE Transactions on Computers, vol. C-23, no. 10, pp. 1078-1092, 1974.
3. O. Roig, J. Cortadella, M. A. Peiia, and E. Pastor, "Automatic generation of synchronous test patterns for asynchronous circuits," in Proceedings of the 34th Design Automation Conference, 1997, pp. 620-625.
4. E. B. Eichelberger, "Hazard detection in combinational and sequential switching circuits," IBM Journal of Research and Development, vol. 9, no. 2, pp. 90-99, 1965.
5. T. J. Chakraborty, V. D. Agrawal, and M. L. Bushnell, "Delay fault models and test generation for random logic sequential circuits," in Proceedings of the 29th Design Automation Conference, 1992, pp. 165-172.
6. S. Sur-Kolay, M. Roncken, K Stevens, P. P. Chaudhuri, and R. Roy, "Fsimac: A fault simulator for asynchronous sequential circuits," in Proceedings of the 9th Asian Test Symposium, 2000, pp. 114-119.
7. S. Chakraborty, D. Dill, and K. Yun, "Min-max timing analysis and an application to asynchronous circuits," Proceedings of the IEEE, vol. 87, no. 2, pp. 332-346, 1999.
8. W. A. Clark, "Macromodular computer systems," in Proceedings of the Spring Joint Computer Conference, AFIPS, 1967, vol. 30, pp. 335-336.
9. C. J. Myers and T. Meng, "Synthesis of timed asynchronous circuits," IEEE Transactions on VLSI Systems, vol. 1, no. 2, pp. 106-119, 1993.
10. D. Muller and W. Bartky, "A theory of asynchronous circuits," In Annals of Computing Laboratory of Hardward University, pp. 204-243, 1959.
11. C. J. Myers, Asynchronous Circuit Design, John Wiley and Sons, Inc., New York, 2001.
12. S. H. Unger, Asynchronous Sequencial Switching Circuits, Wiley-Interscience, New York, 1969.
13. J. E. Chen, C. L. Lee, and W. J. Shen, "Single-fault fault-collapsing analysis in sequential logic circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 10, no. 12, pp. 1559-1568, 1991.
14. H. K. Lee and D. S. Ha, "Hope: An efficient parallel fault simulator for synchronous sequential circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, no. 9, pp. 1048-1058, 1996.
15. J. Cortadella, M. Kishinevsky, A. Kondratyev, L. Lavagno, and A. Yakovlev, "Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers," IEICE Transactions on Information and Systems, vol. E80-D, no. 3, pp. 315-325, 1997.
16. F. Shi and Y. Makris, "Fault simulation and random test generation for speed-independent circuits," in Proceedings of the 2004 Great Lakes Symposium on VLSI, 2004, pp. 127-130.