Fault simulation and random test generation for speed-independent circuits

Proceedings of the ACM Great Lakes Symposium on VLSI

Volumn , Issue , 2004, Pages 127-130

  Shi, Feng ^a   Makris, Yiorgos ^a  

^a Yale University   (United States)

Author keywords

Asynchronous Circuits; Fault Simulation; Random Test Pattern Generation; Speed Independent Circuits

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRICAL ENGINEERING; FAULT TOLERANT COMPUTER SYSTEMS; PROBABILITY; RANDOM NUMBER GENERATION; SIMULATORS; TIMING CIRCUITS; VECTORS;

ASYNCHRONOUS CIRCUITS; FAULT SIMULATION; RANDOM TEST PATTERN GENERATION; SPEED-INDEPENDENT CIRCUITS;

ASYNCHRONOUS SEQUENTIAL LOGIC;

EID: 2942695871     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/988952.988984     Document Type: Conference Paper

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