Synchronous test generation model for asynchronous circuits

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 1996, Pages 178-185

  Banerjee, Savita ^a   Chakradhar, Srimat T ^a   Roy, Rabindra K ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DELAY CIRCUITS; FAILURE ANALYSIS; GRAPH THEORY; INTEGRATED CIRCUIT TESTING; LOGIC GATES; MATHEMATICAL MODELS; TIMING CIRCUITS; VLSI CIRCUITS;

ASYNCHRONOUS CIRCUITS; COMBINATIONAL LOGIC; FAULT SIMULATION; SIGNAL TRANSITION GRAPHS; SYNCHRONOUS TEST GENERATION MODEL;

SEQUENTIAL CIRCUITS;

EID: 0029697592     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)