Minimizing pattern count for interconnect test under a ground bounce constraint

IEEE Design and Test of Computers

Volumn 20, Issue 2, 2003, Pages 8-18

  Marinissen, Erik Jan ^a   Vermeulen, Bart ^a   Hollmann, Henk ^a   Bennetts, R G ^b  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b Bennetts Associates   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; INTERCONNECTION NETWORKS; PRINTED CIRCUIT BOARDS; SWITCHING; SYNCHRONIZATION;

SIMULATANEOUSLY-SWITCHING-OUTPUTS LIMIT (SSOL);

DEGREES OF FREEDOM (MECHANICS);

EID: 0037341498     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2003.1188257     Document Type: Article

References (12)

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10. E.J. Marinissen, B. Bennetts, and B. Vermeulen, "Incorporating a Ground-Bounce Preventing Constraint Into Wiring Interconnect Test Pattern Generation Algorithms," Proc. IEEE Int'l Board Test Workshop (BTW 02), 2002; http://www.dft.co.uk/BTW02/btw02-1-3.pdf.
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