Novel control pattern generators for interconnect testing with boundary scan

IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 1999, Pages 112-120

  Feng, Wenyi ^a   Meyer, Fred J ^a   Lombardi, Fabrizio ^a  

^a NOKIA RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; SHORT CIRCUIT CURRENTS;

BOUNDARY SCAN; CONTROL PATTERN TEST GENERATORS (CPTG); DATA PATTERN TEST GENERATORS (DPTG);

INTERCONNECTION NETWORKS;

EID: 0033321401     PISSN: 10636722     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)