Switching activity generation with automated BIST synthesis for performance testing of interconnects

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 20, Issue 9, 2001, Pages 1143-1158

  Pendurkar, Rajesh ^a,b   Chatterjee, Abhijit ^a,c   Zorian, Yervant ^a,d  

^a IEEE   (United States)

^b SUN MICROSYSTEMS   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d LogicVision Inc   (United States)

Author keywords

BIST; Design for testability; Interconnect performance test; Markov model; Nonlinear feedback shift register; Switching activity

Indexed keywords

NONLINEAR FEEDBACK;

BUILT-IN SELF TEST; CROSSTALK; DESIGN FOR TESTABILITY; GENETIC ALGORITHMS; MARKOV PROCESSES; MATHEMATICAL MODELS; OPTIMIZATION; SHIFT REGISTERS; SWITCHING;

INTEGRATED CIRCUIT TESTING;

EID: 0035441029     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.945309     Document Type: Article

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