Configuration free SoC interconnect BIST methodology

IEEE International Test Conference (TC)

Volumn , Issue , 2001, Pages 1033-1038

  Su, Chauchin ^a   Tseng, Wenliang ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT-IN SELF TEST; COMPUTER HARDWARE; DESIGN FOR TESTABILITY; PRINTED CIRCUIT BOARDS; SHIFT REGISTERS;

AUTOMATIC TEST EQUIPMENTS (ATE); SYSTEM ON CHIP (SOC);

CHIP SCALE PACKAGES;

EID: 0035687725     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (10)

1. Testing and diagnosis of interconnects using boundary scan architecture
2. Diagnosis for wiring interconnects
3. An universal BIST methodology for interconnects
4. On the design of self-checking boundary scanable boards
5. An IDDQ based built-in concurrent test technique for interconnects in a boundary scan environment
6. Decentralized BIST methodology for system level interconnects
7. Applications of the IEEE P1149.5 module test and maintenance bus