High performance memory mode control for HDTV decoders

IEEE Transactions on Consumer Electronics

Volumn 49, Issue 4, 2003, Pages 1348-1353

  Park, Seong Il ^a   Yi, Yongseok ^a   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

HDTV decoder; History based prediction; Memory controller; Memory performance; Synchronous memory

Indexed keywords

BANDWIDTH; COMPUTER ARCHITECTURE; COMPUTER HARDWARE; HIGH DEFINITION TELEVISION; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); MULTIMEDIA SYSTEMS; VLSI CIRCUITS;

AUDIO DECODER; HIGH PERFORMANCE MEMORY MODE CONTROL; SYNCHRONOUS DYNAMIC RANDOM ACCESS STORAGE; SYSTEM-ON-CHIP DESIGN;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 1542647459     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2003.1261239     Document Type: Article

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