Architecture and memory requirements for stand-alone and hierarchical MPEG2 HDTV-decoders with synchronous DRAMs

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1995, Pages 609-612

  Winzker, Marco ^a   Pirsch, Peter ^a   Reimers, Jochen ^a  

^a LEIBNIZ UNIVERSITY HANNOVER   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER STORAGE; COMMUNICATION CHANNELS (INFORMATION THEORY); HIERARCHICAL SYSTEMS; HIGH DEFINITION TELEVISION; IMAGE COMMUNICATION SYSTEMS; IMAGE COMPRESSION; IMAGE PROCESSING; INTERFACES (COMPUTER); RANDOM ACCESS STORAGE; TELEVISION STANDARDS;

HIGH DEFINITION TELEVISION DECODER; SYNCHRONOUS DIGITAL RANDOM ACCESS MEMORY; VIDEO MEMORY; VIDEO PROCESSING UNIT;

DECODING;

EID: 0029194177     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)