Multi-thread VLIW processor architecture for HDTV decoding

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2000, Pages 559-562

  Kim, Hansoo ^a   Yang, Woo Seung ^a   Shin, Myoung Cheol ^a   Min, Seung Jai ^b   Bae, Seong Ok ^b   Park, In Cheol ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b LG   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

MOVING PICTURE EXPERTS GROUP; MULTITHREAD PROCESSOR ARCHITECTURE; VERY LONG INSTRUCTION WORD PROCESSOR;

ALGORITHMS; COMPUTER ARCHITECTURE; DIGITAL SIGNAL PROCESSING; HIGH DEFINITION TELEVISION; IMAGE CODING; IMAGE COMPRESSION; INTEGRATED CIRCUIT LAYOUT; INTERFACES (COMPUTER); VLSI CIRCUITS;

MICROPROCESSOR CHIPS;

EID: 0033713493     PISSN: 08865930     EISSN: None     Source Type: Journal    
DOI: 10.1109/CICC.2000.852730     Document Type: Article

References (5)

1. K. Tsunashima K. Muneishi H. Morikawa H. Kayashima V. Sinyanskiy An integrated DTV receiver for ATSC digital television standard IEEE transaction on consumer electronics 667 671 1998
2. R. Sita E. Brosz R. Meyer L. Philips R. T. Ryan A single-chip HDTV video decoder design IEEE transaction on consumer electronics 519 526 1998
3. Y. Okada An 80mm2 MPEG2 Audio/Video decode LSI ISSCC Digest of Technical Papers ISSCC Digest of Technical Papers 1997-Feb.
4. S.-O. Bae K.-S. Kim Symbol parallel VLC decoding architecture for HDTV application 1998 Digest of technical papers of ICCE 1998 Digest of technical papers of ICCE 1998
5. S.-O. Bae S.-J. Min A computationally efficient IDCT algorithm Proceeding of MWCAS'97 2 973 976 Proceeding of MWCAS'97 1998