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Volumn 45, Issue 3, 1999, Pages 879-883

A cost effective HDTV decoder IC with integrated system controller, down converter, graphics engine and display processor

Author keywords

[No Author keywords available]

Indexed keywords


EID: 1542730414     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/30.793631     Document Type: Article
Times cited : (2)

References (6)
  • 1
    • 0032135937 scopus 로고    scopus 로고
    • Minimum Drift Architectures for 3-Layer Scalable DTV Decoding
    • August
    • A. Vetro, H. Sun, P. Da Graca, T. Poon, "Minimum Drift Architectures for 3-Layer Scalable DTV Decoding", IEEE Transactions on Consumer Electronics, vol. 44, no. 3, pp527-536, August 1998.
    • (1998) IEEE Transactions on Consumer Electronics , vol.44 , Issue.3 , pp. 527-536
    • Vetro, A.1    Sun, H.2    Da Graca, P.3    Poon, T.4
  • 4
    • 33747790408 scopus 로고    scopus 로고
    • National Association of Broadcasters Press Release Washington, DC; February 4
    • "Broadcasters: Delivering on Digital Television"; National Association of Broadcasters Press Release; Washington, DC; February 4, 1999.
    • (1999) Broadcasters: Delivering on Digital Television
  • 6
    • 33747783352 scopus 로고
    • Architecture and Implementation of IC's for a DSC-HDTV Video Decoder System
    • Oct.
    • Duardo, O., et. al., "Architecture and Implementation of IC's for a DSC-HDTV Video Decoder System", IEEE Micro, Oct. 1992.
    • (1992) IEEE Micro
    • Duardo, O.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.