HIGH PERFORMANCE AND COST EFFECTIVE MEMORY ARCHITECTURE FOR AN HDTV DECODER LSI

ICASSP, IEEE International Conference on Acoustics, Speech and Signal Processing - Proceedings

Volumn 4, Issue , 1999, Pages 1981-1984

  Takizawa, Tetsuro ^a   Tujiine, Junji ^a   Harasaki, Hidenobu ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; DECODING; HIGH DEFINITION TELEVISION; MAPPING; MEMORY ARCHITECTURE;

COMPRESSION METHODS; COST EFFECTIVE; FORMAT CONVERSION; FRAME MEMORY; HIGH COSTS; HIGH MEMORY BANDWIDTH; MEMORY COMPRESSION; MEMORY COST; MEMORY MAPPING; PERFORMANCE;

COST EFFECTIVENESS;

EID: 0000906881     PISSN: 15206149     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICASSP.1999.758315     Document Type: Conference Paper

References (7)

1. O. Duardo, et al.: "AN HDTV VIDEO CODER IC FOR ATV RECEIVERS," IEEE Trans, on Consumer Electronics, Vol. 43, No. 3, pp.628-632, 1997.
2. R.Sita, etal.: "A SINGLE CHIP HDTV VIDEO DECODER DESIGN," Proc. of ICCE'98, pp.50-51, 1998.
3. Rambus Inc.: "64M/72M Direct RDRAM Data Sheet," DL-0035, http://www.rambus.com/, pp. 1-62, 1998.
4. R. Clisp: "Direct Rambus Technology: The Next Main Memory Standard," IEEE Micro, Vol. 17, No. 6, pp.18-28, 1997.
5. U. Bayazit, et al.: "A NOVEL MEMORY COMPRESSION SYSTEM FOR MPEG-2 DECODERS," Proc. of ICCE'98, pp.56-57, 1998.
6. R. Bruni et al.: "A NOVEL ADAPTIVE VECTOR QUANTIZATION METHOD FOR MEMORY REDUCTION IN MPEG-2 HDTV DECODERS," Proc. of ICCE'98, pp.58-59, 1998.
7. P. With, et al.: "An MPEG Decoder with Embedded Compression for Memory Reduction," Proc. of ICCE'98, pp.60-61, 1998.