A dynamic-SDRAM-mode-control scheme for low-power system with a 32-bit RISC CPU

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2001, Pages 358-363

  Miura, S ^a   Ayukawa, K ^a   Watanabe, T ^a  

^a HITACHI LTD   (Japan)

Author keywords

Active standby mode; SDRAM controller; Standby mode

Indexed keywords

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; CONTROL EQUIPMENT; PERSONAL DIGITAL ASSISTANTS;

LOW POWER SYSTEMS;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0034869649     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. Sub-1- μ a dynamic reference voltage generator for battery-operated DRAMs
2. Trends in low-power RAM circuit technologies
3. 250mV bit-line swing scheme for a 1V 4Gb DRAM
4. Circuit design techniques for low-voltage operation and/or giga-scale DRAMs
5. Access optimizer to overcome the future walls of embedded DRAMs in the era of systems on silicon
6. A DRAM system for consistently reducing CPU wait cycles
7. A memory access system for merged memory with logic LSIs