Crosstalk noise estimation for generic RC trees

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 110-116

  Takahashi, M ^a   Hashimoto, M ^a   Onodera, H ^a  

^a KYOTO UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COUPLED CIRCUITS; CROSSTALK; EQUIVALENT CIRCUITS; ERROR ANALYSIS; MATHEMATICAL TRANSFORMATIONS; PARAMETER ESTIMATION; TREES (MATHEMATICS); WAVEFORM ANALYSIS;

PARTIALLY-COUPLED INTERCONNECTS;

SPURIOUS SIGNAL NOISE;

EID: 0035191787     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's
2. Delay and noise formulas for capacitively coupled distributed RC lines
3. Crosstalk reduction for VLSI
4. An approach to the analysis and detection of crosstalk faults in digital VLSI circuits
5. Efficient coupled noise estimation for on-chip interconnects
6. Predicting coupled noise in RC circuits by matching 1, 2, and 3 moments
7. Crosstalk in VLSI interconnections
8. Improved crosstalk modeling for noise constrained interconnect optimization
9. An effective capacitance based delay metric for RC interconnect
10. Modeling the driving-point characteristic of resistive interconnect for accurate delay estimation