Analysis and reduction of capacitive coupling noise in high-speed VLSI circuits

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2001, Pages 104-109

  Heydari, Payam ^a   Pedram, Massoud ^b  

^a University of California at Irvine   (United States)

^b University of Southern California   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; COUPLED CIRCUITS; CROSSTALK; ERROR ANALYSIS; SPURIOUS SIGNAL NOISE; TIME DOMAIN ANALYSIS; TRANSISTORS; WAVEFORM ANALYSIS;

CAPACITIVE COUPLING NOISE;

VLSI CIRCUITS;

EID: 0035183799     PISSN: 10636404     EISSN: None     Source Type: Journal    
DOI: 10.1109/ICCD.2001.955011     Document Type: Article

References (10)

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5. Balanced truncation with spectral shaping for RLC interconnects
6. Crosstalk reduction for VLSI
7. Crosstalk in VLSI interconnections
8. Efficient coupled noise estimation for on-chip interconnects
9. Buffer insertion for noise and delay optimization