The evolution of DRAM cell technology

Solid State Technology

Volumn 40, Issue 5, 1997, Pages 89-101

  El Kareh, B ^a,b   Bronner, G B ^b,c,d,e,f   Schuster, S E ^b,f,g,h  

^a IBM MICROELECTRONICS   (United States)

^b IBM   (United States)

^c BROWN UNIVERSITY   (United States)

^d STANFORD UNIVERSITY   (United States)

^e Brown University ^*

^f IEEE

^g NEW YORK UNIVERSITY   (United States)

^h IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 0002656303     PISSN: 0038111X     EISSN: None     Source Type: Trade Journal    
DOI: None     Document Type: Article

References (6)

1. B. Prince, Semiconductor Memories, John Wiley & Sons, New York, 1991.
2. C.G. Sodini, T.I. Kamins, "Enhanced Capacitor for One-Transistor Memory Cell," IEEE Trans. Electron Dev., ED-23, pp. 185-1190, 1976.
3. G.B. Bronner, "DRAM Technology Trends for 256 Mbit and Beyond," 1996 International Electron Devices and Materials Symposium, Symposium A, Hsinchu, Taiwan, pp. 75-82, Dec. 1996.
4. K.P. Muller, et al., "Trench Storage Node Technology for Gigabit DRAM Generations," 1996 IEDM Digest of technical Papers, pp. 507-510, 1996.
5. J.G. Ryan, R.M. Geffken, N.R. Poulin, and J.R. Paraszczak, "The Evolution of Interconnection Technology at IBM," J. Res. Dev., 39 (4), pp. 371-381, 1995.
6. S.E. Schuster, "Multiple Word/Bit Line Redundancy for Semiconductor Memories," IEEE J. Solid State Circuits, SC-13 (5), pp. 698-703, 1978.