Analytical analysis of finite cache penalty and cycles per instruction of a multiprocessor memory hierarchy using miss rates and queuing theory

IBM Journal of Research and Development

Volumn 45, Issue 6, 2001, Pages 819-842

  Matick, Richard E ^a   Heller, Thomas J ^b   Ignatowski, Michael ^b  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPROXIMATION THEORY; HIERARCHICAL SYSTEMS; MATHEMATICAL MODELS; MULTIPROCESSING SYSTEMS; QUEUEING THEORY; SPREADSHEETS;

FINITE CACHE PENALTY;

CACHE MEMORY;

EID: 0035516569     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.456.0819     Document Type: Article

References (13)

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6. Power4 focus on memory bandwidth
7. Architecture implications in the design of microprocessors