메뉴 건너뛰기




Volumn 89, Issue 11, 2001, Pages 1560-1575

Microarchitectural innovations: Boosting microprocessor performance beyond semiconductor technology scaling

Author keywords

Branch prediction; High performance microprocessors; Memory dependence speculation; Microarchitecture; Out oforder execution; Speculative execution; Thread level speculation

Indexed keywords


EID: 0141896323     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/5.964438     Document Type: Article
Times cited : (22)

References (72)
  • 1
    • 0004348513 scopus 로고
    • Architecture of the Pentium microprocessor
    • D. Alpert and D. Avnon, Architecture of the Pentium microprocessor, IEEE Micro, vol. 13, no, 3, pp. 11-21, 1993.
    • (1993) IEEE Micro , vol.13 , Issue.3 , pp. 11-21
    • Alpert, D.1    Avnon, D.2
  • 2
    • 2842517957 scopus 로고
    • The IBM system/360 model 91: Machine philosophy and instruction-handling
    • Jan.
    • D. W. Anderson, F. J. Sparacio, and R. M. Tomasulo, The IBM system/360 model 91: Machine philosophy and instruction-handling, IBM J. Res. Develop., pp. 8-24, Jan. 1967.
    • (1967) IBM J. Res. Develop. , pp. 8-24
    • Anderson, D.W.1    Sparacio, F.J.2    Tomasulo, R.M.3
  • 3
    • 0033321638 scopus 로고    scopus 로고
    • DIVA: A reliable substrate for deep submicron design
    • Dec.
    • T. Austin, DIVA: A reliable substrate for deep submicron design, in Proc. Annu. Int. Symp. Microarchitecture, Dec. 1999, pp. 196-207.
    • (1999) Proc. Annu. Int. Symp. Microarchitecture , pp. 196-207
    • Austin, T.1
  • 9
    • 0033362679 scopus 로고    scopus 로고
    • Technology and design challenges for low power and high performance
    • Aug.
    • V. De and S. Borkar, Technology and design challenges for low power and high performance, in Proc. Int. Symp. Low Power Electronics and Design, Aug. 1999, pp. 163-168.
    • (1999) Proc. Int. Symp. Low Power Electronics and Design , pp. 163-168
    • De, V.1    Borkar, S.2
  • 11
  • 14
    • 0007997616 scopus 로고    scopus 로고
    • ARB: A hardware mechanism for dynamic memory disambiguation
    • May
    • M. Franklin and G. S. Sohi, ''ARB: A hardware mechanism for dynamic memory disambiguation, IEEE Trans. Comput., vol. 45, pp. 552-571. May 1996.
    • (1996) IEEE Trans. Comput. , vol.45 , pp. 552-571
    • Franklin, M.1    Sohi, G.S.2
  • 15
    • 33646924765 scopus 로고    scopus 로고
    • Speculative execution based on value prediction, EE Dept., Technion-Israel Inst. Technology
    • Nov.
    • F. Gabbay and A. Medelson, Speculative execution based on value prediction, EE Dept., Technion-Israel Inst. Technology, Tech. Rep. TR-1080, Nov. 1996.
    • (1996) Tech. Rep. TR-1080
    • Gabbay, F.1    Medelson, A.2
  • 17
    • 0025232231 scopus 로고
    • Machine organization of the IBM RISC system/ 6000 processor
    • Jan.
    • G. F. Grohoski, Machine organization of the IBM RISC system/ 6000 processor, IBM J. Res. Develop., vol. 34, pp. 37-58, Jan. 1990.
    • (1990) IBM J. Res. Develop. , vol.34 , pp. 37-58
    • Grohoski, G.F.1
  • 18
    • 0030712582 scopus 로고    scopus 로고
    • A gate-level leakage power reduction method for ultra-low-power CMOS circuits
    • May
    • J. P. Halter and F. N. Najm, A gate-level leakage power reduction method for ultra-low-power CMOS circuits, in Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 475-478.
    • (1997) Proc. IEEE Custom Integrated Circuits Conf. , pp. 475-478
    • Halter, J.P.1    Najm, F.N.2
  • 20
    • 85023980169 scopus 로고
    • Advanced performance features of the 64-bit PA-8000
    • Mar.
    • D. Hunt, Advanced performance features of the 64-bit PA-8000, in Proc. COMPCON'95, Mar. 1995, pp. 123-128.
    • (1995) Proc. COMPCON'95 , pp. 123-128
    • Hunt, D.1
  • 21
    • 0022584031 scopus 로고
    • HPSm, a high performance restricted data flow architecture having minimal functionality
    • June
    • W. W. Hwu and Y. N. Patt, HPSm, a high performance restricted data flow architecture having minimal functionality, in Proc. 13th Itu. Symp. Computer Architecture. June 1986, pp. 297-307.
    • (1986) Proc. 13th Itu. Symp. Computer Architecture. , pp. 297-307
    • Hwu, W.W.1    Patt, Y.N.2
  • 22
    • 0023587656 scopus 로고
    • Checkpoint repair for high-performance out-of-order execution machines
    • Dec.
    • _, Checkpoint repair for high-performance out-of-order execution machines, IEEE Trans. Cornput., vol. C-36, pp. 1496-1514, Dec. 1987.
    • (1987) IEEE Trans. Cornput. , vol.VOL. C-36 , pp. 1496-1514
  • 23
    • 0345529559 scopus 로고
    • Englewood Cliffs, NJ: PrenticeHall
    • M. Johnson, Superscalar Design. Englewood Cliffs, NJ: PrenticeHall, 1990.
    • (1990) Superscalar Design.
    • Johnson, M.1
  • 24
    • 0025429331 scopus 로고
    • Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers
    • May
    • N. P. Jouppi, Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers, in P rue. 17th Anna. Int. Symp. Computer Architecture, May 1990, pp. 364-373.
    • (1990) P Rue. 17th Anna. Int. Symp. Computer Architecture , pp. 364-373
    • Jouppi, N.P.1
  • 25
    • 0030129806 scopus 로고    scopus 로고
    • The MIPS R10000 superscalar microprocessor
    • Apr.
    • K. Yeager, The MIPS R10000 superscalar microprocessor, IEEE Micro, vol. 16, pp. 28-40, Apr. 1996.
    • (1996) IEEE Micro , vol.16 , pp. 28-40
    • Yeager, K.1
  • 26
    • 0026156263 scopus 로고
    • Branch history table prediction of moving targets due to subroutine returns
    • May
    • D. Kaeu and P. Emma, Branch history table prediction of moving targets due to subroutine returns, in Proc. 18th Int. Symp. Computer Architecture, May 1991, pp. 34-42.
    • (1991) Proc. 18th Int. Symp. Computer Architecture , pp. 34-42
    • Kaeu, D.1    Emma, P.2
  • 30
    • 0019892368 scopus 로고
    • Lockup-free instruction fetch/prefetch cache organization
    • May
    • D, Kroft, Lockup-free instruction fetch/prefetch cache organization, in Proc. 8th Int. Syrup. Computer Architecture, May 1981, pp. 81-87.
    • (1981) Proc. 8th Int. Syrup. Computer Architecture , pp. 81-87
    • Kroft, D.1
  • 31
    • 0021204160 scopus 로고
    • Branch prediction strategies and branch target buffer design
    • Jan.
    • [311 J. K. F. Lee and A. J. Smith, Branch prediction strategies and branch target buffer design, IEEE Comput., vol. 17, Jan. 1984.
    • (1984) IEEE Comput. , vol.17
    • Lee F, J.K.1    Smith, A.J.2
  • 32
  • 35
    • 0031232922 scopus 로고    scopus 로고
    • Will physical scalability sabotage performance gains?
    • Sept.
    • D. Matzke, Will physical scalability sabotage performance gains?, Computer, vol. 30, pp. 37-39, Sept. 1997.
    • (1997) Computer , vol.30 , pp. 37-39
    • Matzke, D.1
  • 36
    • 0003506711 scopus 로고
    • Digital Equipment Corp.. WRU Tech. Rep. TN-36. June
    • S. McFarling, Combining branch predictors, Digital Equipment Corp.. WRU Tech. Rep. TN-36. June 1993.
    • (1993) Combining Branch Predictors
    • McFarling, S.1
  • 37
    • 0002662988 scopus 로고
    • The Alpha AXP architecture and 21 064 processor
    • June
    • E. McLellan, The Alpha AXP architecture and 21 064 processor, IEEE.Micro, pp. 36-47, June 1993.
    • (1993) IEEE.Micro , pp. 36-47
    • McLellan, E.1
  • 38
    • 0005359842 scopus 로고
    • Interconnect performance limits on gigascale integration (GSI)
    • J. D. Meindl and J. Davis, interconnect performance limits on gigascale integration (GSI), Mater. Chem. Pliys., vol. 41, pp. 161-166, 1995.
    • (1995) Mater. Chem. Pliys. , vol.41 , pp. 161-166
    • Meindl, J.D.1    Davis, J.2
  • 39
    • 0003590419 scopus 로고    scopus 로고
    • Ph.D. dissertation, Univ. Wisconsin-Madison, Madison. Wl. Dec.
    • A. Moshovos, Memory dependence prediction, Ph.D. dissertation, Univ. Wisconsin-Madison, Madison. Wl. Dec. 1998.
    • (1998) Memory Dependence Prediction
    • Moshovos, A.1
  • 42
    • 0026918390 scopus 로고
    • Improving the accuracy of dynamic branch prediction using branch correlation
    • Oct.
    • S.-T. Pan, K. So, and J. T. Rahmch, Improving the accuracy of dynamic branch prediction using branch correlation, in Proc: 5th Int. Conf, Architectural Support for Programming Languages and Operating Systems, Oct. 1992, pp. 76-84.
    • (1992) Proc , vol.5 , pp. 76-84
    • Pan, S.-T.1    So, K.2    Rahmch, J.T.3
  • 44
    • 0022289981 scopus 로고
    • HPS, a new microarchilecture: Rationale and introduction
    • Pacific Grove, CA, Dec.
    • Y. N. Patt. W. W. Hwu, and M. Shebanow, HPS, a new microarchilecture: Rationale and introduction, in Proc. 18th Annu. Workshop Microprogramming, Pacific Grove, CA, Dec. 1985, pp. 103-108.
    • (1985) Proc. 18th Annu. Workshop Microprogramming , pp. 103-108
    • Patt, Y.N.1    Hwu, W.W.2    Shebanow, M.3
  • 46
    • 0032597692 scopus 로고    scopus 로고
    • AR-SMT: A microarchitectural approach to fault tolerance in microprocessors
    • June
    • F.. Rotenberg, AR-SMT: A microarchitectural approach to fault tolerance in microprocessors, in Proc. 29th Int. Symp. Fault-Tolerant Computing, June 1999, pp. 84-91.
    • (1999) Proc. 29th Int. Symp. Fault-Tolerant Computing , pp. 84-91
    • Rotenberg, F.1
  • 49
    • 0032669611 scopus 로고    scopus 로고
    • Improving virtual function call target prediction via dependence-based pre-computation
    • June
    • _, Improving virtual function call target prediction via dependence-based pre-computation, in Proc. Int. Conf. Supercompuiing, June 1999, pp. 356-364.
    • (1999) Proc. Int. Conf. Supercompuiing , pp. 356-364
  • 53
    • 0020177251 scopus 로고
    • Cache memories
    • A. J. Smith, Cache memories, ACM Comput. Surv., vol. 14, no. 3, pp. 473-530, 1982.
    • (1982) ACM Comput. Surv. , vol.14 , Issue.3 , pp. 473-530
    • Smith, A.J.1
  • 54
    • 0024013595 scopus 로고
    • Implementing precise Interrupts in pipelined processors
    • May
    • J. Smith and A. Pleszkim, Implementing precise Interrupts in pipelined processors, IEEE 'Irans. Comput., vol. 37, pp. 562-573, May 1988.
    • (1988) IEEE 'Irans. Comput. , vol.37 , pp. 562-573
    • Smith, J.1    Pleszkim, A.2
  • 58
    • 0025401087 scopus 로고
    • Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers,'
    • Mar.
    • G. S. Sohi, Instruction issue logic for high-performance, interruptible, multiple functional unit, pipelined computers,' IEEE Trans. Comput., vol. 39, pp. 349-359, Mar. 1990.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 349-359
    • Sohi, G.S.1
  • 59
    • 0029178210 scopus 로고
    • Multiscalar processors
    • June
    • G. S. Sohi, S. E. Breach, and T. Vijaykumar, Multiscalar processors, in Proc. 22nd Annu. Int. Svmp. Computer Architecture, June 1995, pp. 414-425.
    • (1995) Proc. , vol.22 , pp. 414-425
    • Sohi, G.S.1    Breach, S.E.2    Vijaykumar, T.3
  • 61
    • 0004174428 scopus 로고    scopus 로고
    • Dept. EE Systems, Univ. Southern California, Tech. Rep. CENG-98-25, Oct.
    • Y. Song and M. Dubois, Assisted execution, Dept. EE Systems, Univ. Southern California, Tech. Rep. CENG-98-25, Oct. 1998.
    • (1998) Assisted execution
    • Song, Y.1    Dubois, M.2
  • 63
    • 85042605140 scopus 로고
    • Parallel operation in die control data 6600
    • J. E. Thorton, Parallel operation in die control data 6600, in Proc. AFIPS Fall Joint Computer Conf. vol. 26. 1964, pp. 33-40.
    • (1964) Proc. AFIPS Fall Joint Computer Conf. , vol.26 , pp. 33-40
    • Thorton, J.E.1
  • 64
    • 0003081830 scopus 로고
    • An efficient algorithm for exploiting multiple arithmetic units
    • Jan.
    • [64- R. M. Tomasuio, An efficient algorithm for exploiting multiple arithmetic units, IBM J. Res. Develop., pp. 25-33, Jan. 1967.
    • (1967) IBM J. Res. Develop., Pp. , pp. 25-33
    • Tomasuio, R.M.1
  • 65
    • 0034316177 scopus 로고    scopus 로고
    • The MAJC architecture: A synthesis of parallelism and scalability
    • Nov.-Dec.
    • M. Tremblay, J. Chan, S. Chaudhry. A. W. Conigliaro, and S. S. Tse, The MAJC architecture: A synthesis of parallelism and scalability, IEEE Micro, pp. 12-25, Nov.-Dec. 2000.
    • (2000) IEEE Micro , pp. 12-25
    • Tremblay, M.1    Chan, J.2    Chaudhry, S.3    Conigliaro, A.W.4    Tse, S.S.5
  • 67
    • 0042596411 scopus 로고
    • Slave memories and dynamic storage allocation
    • Apr.
    • M. Wilkes, Slave memories and dynamic storage allocation, IEEE Trans. Electron. Comput., pp. 270-271, Apr. 1965.
    • (1965) IEEE Trans. Electron. Comput. , pp. 270-271
    • Wilkes, M.1
  • 70
    • 0026961839 scopus 로고
    • A comprehensive instraction fetch mechanism for a processor supporting speculative execution
    • T.-Y. Yeh and Y N. Patt, A comprehensive instraction fetch mechanism for a processor supporting speculative execution, in Proc. 25th Anna. Int. Symp. Microarchitecture, Dec. 1992, pp. 129-139.
    • (1992) Proc. 25th Anna. Int. Symp. Microarchitecture, Dec. , pp. 129-139
    • Yeh, T.-Y.1    Patt, Y.N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.