Time Memory Cell VLSI for the PHENIX Drift Chamber

IEEE Transactions on Nuclear Science

Volumn 45, Issue 3 PART 1, 1998, Pages 735-739

  Arai, Y ^a   Ikeno, M ^a   Sagara, M ^a   Emura, T ^a  

^a INSTITUTE OF PARTICLE AND NUCLEAR STUDIES   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DATA TRANSFER; INTEGRATED CIRCUIT MANUFACTURE; ONLINE SYSTEMS; OSCILLATORS (ELECTRONIC); PATTERN RECOGNITION; PHASE LOCKED LOOPS;

ASYMMETRIC RING OSCILLATOR; DELAY LOCKED LOOP; TIME TO DIGITAL CONVERTERS;

VLSI CIRCUITS;

EID: 0032097338     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.682626     Document Type: Article

References (9)

1. TMC home page, "http://www-atlas.kek.jp/~araiy/".
2. Y. Arai and T. Matsumura and K. Endo; "A CMOS 4 ch x l k Time MemoryLSI with 1 ns/bit Resolution", IEEE J. of Solid-State Circuits, Vol.27, No.3, 1992, pp. 359-364.
3. Y. Arai andM. Ikeno; "A Time Digitizer CMOS Gate-Array with a 250 ps Time Resolution", IEEE J. of Solid-State Circuits, Vol. 31, No. 2, 1996, pp. 212-220
4. Y. Arai and M. Ikeno; "A 64-ch Time Memory Cell Module with aDSP and a VME Interface", EEEETrans. on Nucl. Sei. Vol. 41, No. 4, 1994, pp. 1187-1191.
5. H. Shirasu, Y. Arai, M. Ikeno, T. MurataandT. Emura;"A VME 32 ch Pipeline TDC Module with TMC LSIs", IEEE Trans, on Nucl. Sei. Vol. 43, No. 3,1996, pp. 1799-1803.
6. J. Christiansen, et al.; "An Integrated 16 channel CMOS Time to Digital Converter", IEEE Trans, on Nucl. Sei., Vol. 41, No. 4, 1994, pp. 1104-1108.
7. P.Andreani et al.; "MHITIC: 8-channels, 1-ns, multi-hit time-to-digital converter CMOS integrated circuit", Proc. of ESSCIRC '96, 1996, pp. 76-79.
8. D.M. Santos, et al.; "A CMOS Delay Locked Loop and Sub-Nanosecond Time-to-Digital Converter Chip", IEEE Trans, on Nucl. Sei., Vol. 43, No. 3, 1994, pp. 1717-1719.
9. "Voltage-Controlled Oscillating Circuit" Patent No. 2663397 (Japan), No. 08/380,580 (USA), No. 95300652.5 (EPC).