An integrated approach to reducing power dissipation in memory hierarchies

Proceedings of the 2002 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES '02

Volumn , Issue , 2002, Pages 88-97

  Pisharath, Jayaprakash ^a   Choudhary, Alok ^a  

^a Northwestern University   (United States)

Author keywords

Dynamic cache; Energy delay product; Energy Saver Buffers (ESB); Integrated approach; Power; RDRAM

Indexed keywords

DYNAMIC CACHE; ENERGY CONSUMPTION; ENERGY DELAY PRODUCT; IN-BETWEEN; INTEGRATED APPROACH; KEY FACTORS; L2 CACHE; LOW POWER; MAIN MEMORY; MEMORY DESIGN; MEMORY HIERARCHY; MEMORY MODULES; MEMORY SYSTEMS; ON CHIP MEMORY; POWER MODES; POWER-AWARE; REDUCING POWER; RESYNCHRONIZATION;

EMBEDDED SYSTEMS; INTEGRATED CONTROL; PROGRAM COMPILERS; STRESS INTENSITY FACTORS; SYNTHESIS (CHEMICAL);

CACHE MEMORY;

EID: 13144281552     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/581630.581645     Document Type: Conference Paper

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