A novel segmented parabolic sine approximation for direct digital frequency synthesizers

Proceedings of the International Conference on Embedded Systems and Applications ESA'04 - Proceedings of the International Conference on VLSI, VLSI'04

Volumn , Issue , 2004, Pages 523-529

  Betowski, David J ^a   Dwyer, Daniel ^a   Beiu, Valeriu ^a  

^a Washington State University   (United States)

Author keywords

Digital Signal Processing; Direct Digital Frequency Synthesizer (DDFS); Low Power Design; Sine Wave Approximation; Vlsi Systems

Indexed keywords

APPROXIMATION THEORY; COMPUTATIONAL COMPLEXITY; DIGITAL SIGNAL PROCESSING; ELECTRIC POWER UTILIZATION; FREQUENCY MULTIPLYING CIRCUITS; VLSI CIRCUITS;

DIRECT DIGITAL FREQUENCY SYNTHESIZERS (DDFS); LOW POWER DESIGN; SINE WAVE APPROXIMATION; VLSI SYSTEMS;

FREQUENCY SYNTHESIZERS;

EID: 12744255435     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (19)

1. D. Betowski and V. Beiu, "Considerations for phase accumulator design for direct digital frequency synthesizers," Proc. Intl. Conf. Neural Networks & Signal Proc. ICNNSP'03, 2003, vol. 1, pp. 176-179.
2. P.-S. Wu and V. Beiu, "On accurate piecewise linear ROM-less direct digital frequency synthesizers," Proc. Intl. Conf. Neural Networks & Signal Proc. ICNNSP'03, 2003, vol. 2, pp. 1595-1599.
3. J. M. P. Langlois and D. Al-Khalili, "Hardware optimized direct digital frequency synthesizer architecture with 60-dBc spectral purity," Proc. Int. Symp. Circ. & Sys. ISCAS'02, 2002, pp. 361-364.
4. J. M. P. Langlois and D. Al-Khalili, "Novel approach to the design of direct digital frequency synthesizers based on linear interpolation," IEEE Trans. Circ. & Sys. II, vol. 50, Sep. 2003, pp. 567-578.
5. A. M. Sodagar and G. R. Lahiji, "Parabolic approximation: A new method for phase-to-amplitude conversion in sine-output direct digital frequency synthesizers," Proc. Int. Symp. Circ. & Sys. ISCAS'00, 2000, vol. 1, pp. 515-518.
6. R. C. Meitzler and W. P. Millard, "A direct digital frequency synthesizer prototype for space applications," Proc. NASA Symp. VLSI Design, 2003. Available: http://www.cambr.uidaho.edu/symposiums/symp11/R. Meitzler_dds_nasa.pdf
7. R. F. Tinder, Engineering Digital Design, Academic Press, 2000, Chp. 3, pp. 79-120.
8. J. Rabaey, A. Chandrakasan, and B. Nikolić, Digital Integrated Circuits. A Design Perspective (2nd edition), Prentice Hall, 2003, Chp. 6, pp. 235-308.
9. R. Zimmerman, "Binary adder architectures for cell-based VLSI and their synthesis," PhD thesis, Swiss Federal Institute of Tech., Zurich, Switzerland, 1997.
10. C. S. Wallace, "A suggestion for a fast multiplier," IEEE Trans. Electr. Comp., vol. EC-13, Feb. 1964, pp. 14-17.
11. S. Vassiliadis and S. D. Coţofanǎ, "7×2 Counters and multiplication with threshold logic." Proc. Asilomar Conf. Signals, Sys., & Comp., vol. 1, Nov. 1996, pp. 192-196.
12. M. Pǎdure, S. D. Coţofaňa, and S. Vassiliadis, "High-speed threshold-boolean logic counters and compressors," Proc. Midwest Symp. Circ. & Sys. MWSCAS'02, vol. 3, Aug. 2002, pp. 457-460.
13. V. Beiu, J. M. Quintana, and M. J. Avedillo, "VLSI implementations of threshold logic: A comprehensive survey," IEEE Trans. Neural Networks, vol. 14, Sep. 2003, pp. 1217-1243.
14. J. Nyathi, V. Beiu, S. Tatapudi, and D. Betowski, "A charge recycling differential noise immune perceptron," Proc. Intl. Joint Conf. Neural Networks, Budapest IJCNN'04, Hungary, Jul. 2004, in press.
15. J. T. Kao, M. Miyazaki, and A. Chandrakasan, "A 175 mV multiply-accumulate unit using an adaptive supply voltage and body bias architecture," IEEE J. Solid-State Circ., vol. 37, Nov. 2002, pp. 1545-1554.
16. H. Soeleman, K. Roy, and B. C. Paul, "Robust subthreshold logic for ultra-low power operation," IEEE Trans. VLSI Sys., vol. 9, Feb. 2001, pp. 90-99.
17. V. Svilan, M. Matsui, and J. Burr, "Energy-efficient 32×32-bit multiplier in tunable near-zero threshold CMOS," Proc. Int. Sym. Low Power Electronics & Design ISLPED'00, Jul. 2000, pp. 268-272.
18. P. Gupta and N. K. Jha, "An algorithm for nano-pipelining of circuits and architectures for a nanotechnology," Proc. Intl. Conf. Design, Automation and Test in Europe DATE'04, Feb. 2004, pp. 974-979.
19. P. Mazumder, S. Kulkarni, M. Bhattacharya, J. P. Sun, and G. Haddad, "Digital circuit applications of resonant tunneling devices," Proc. IEEE, vol. 86, Apr. 1998, pp. 664-686.