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Volumn 3, Issue , 2002, Pages

High-speed hybrid threshold-boolean logic counters and compressors

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; CMOS INTEGRATED CIRCUITS; COUNTING CIRCUITS; TRANSISTORS;

EID: 0036976501     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (10)

References (10)
  • 1
    • 0001342967 scopus 로고
    • Some schemes for parallel multipliers
    • L. Dadda. Some schemes for parallel multipliers. Alta Frequenza, 34:349-356, 1965.
    • (1965) Alta Frequenza , vol.34 , pp. 349-356
    • Dadda, L.1
  • 3
    • 0030211337 scopus 로고    scopus 로고
    • A compact high-speed (31,5) parallel counter circuit based on capacitive Threshold-logic gates
    • August
    • Y. Leblebici, H. Ozdemir, A. Kepkep, and U. Cilingiroglu. A compact high-speed (31,5) parallel counter circuit based on capacitive Threshold-logic gates. IEEE Journal of Solid-State Circuits, 31(8):1177-1183, August 1996.
    • (1996) IEEE Journal of Solid-State Circuits , vol.31 , Issue.8 , pp. 1177-1183
    • Leblebici, Y.1    Ozdemir, H.2    Kepkep, A.3    Cilingiroglu, U.4
  • 7
    • 0024648183 scopus 로고
    • SPIM: A pipelined 64×64-bit iterative multiplier
    • April
    • M Santoro and M. Horowitz. SPIM: a pipelined 64×64-bit iterative multiplier. IEEE Journal of Solid-State Circuits, 24(2):487-493, April 1989.
    • (1989) IEEE Journal of Solid-State Circuits , vol.24 , Issue.2 , pp. 487-493
    • Santoro, M.1    Horowitz, M.2
  • 8
    • 0026218953 scopus 로고
    • Circuit and architecture trade-offs for high-speed multiplication
    • September
    • P. Song and G De Micheli. Circuit and architecture trade-offs for high-speed multiplication. IEEE Journal of Solid-State Circuits, 26(9): 1184-1198, September 1991.
    • (1991) IEEE Journal of Solid-State Circuits , vol.26 , Issue.9 , pp. 1184-1198
    • Song, P.1    De Micheli, G.2
  • 10
    • 0030244775 scopus 로고    scopus 로고
    • 2-1 addition and related operations with Threshold logic
    • September
    • S. Vassiliadis, S. Cotofana, and K. Bertels. 2-1 addition and related operations with Threshold logic. IEEE Transactions on Computers, 45(9): 1062-1068, September 1996.
    • (1996) IEEE Transactions on Computers , vol.45 , Issue.9 , pp. 1062-1068
    • Vassiliadis, S.1    Cotofana, S.2    Bertels, K.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.