Low-cost, on-line software-based self-testing of embedded processor cores

Proceedings - 9th IEEE International On-Line Testing Symposium, IOLTS 2003

Volumn , Issue , 2003, Pages 149-154

  Xenoulis, G ^a   Gizopoulos, D ^a   Kranitis, N ^b   Paschalis, A ^b  

^a UNIVERSITY OF PIRAEUS   (Greece)

^b UNIVERSITY OF ATHENS   (Greece)

Author keywords

Automatic testing; Built in self test; Energy consumption; Fault detection; Hardware; Informatics; Manufacturing; Redundancy; Software testing; System testing

Indexed keywords

AUTOMATIC TESTING; COMPUTER HARDWARE; COSTS; ELECTRIC POWER UTILIZATION; EMBEDDED SYSTEMS; ENERGY UTILIZATION; FAULT DETECTION; HARDWARE; INTEGRATED CIRCUIT TESTING; LIFE CYCLE; MANUFACTURE; REDUNDANCY; SOFTWARE TESTING;

DETECTION CAPABILITY; EMBEDDED PROCESSORS; INFORMATICS; LOW-COST ON-LINE TEST; LOW-POWER CONSUMPTION; NORMAL OPERATIONS; SOFTWARE-BASED SELF-TEST; SYSTEM TESTING;

BUILT-IN SELF TEST;

EID: 11844285816     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214382     Document Type: Conference Paper

References (11)

1. J.Shen, J.Abraham, "Native mode functional test generation for processors with applications to self-test and design validation", in Proc. of IEEE ITC 1998, pp. 990-999.
2. F.Corno, M.Sonza Reorda, G.Squillero, M.Violante, "On the Test of Microprocessor IP Cores", in Proc. of IEEE DATE 2001.
3. Li Chen, S.Dey, "Software-Based Self-Testing Methodology for Processor Cores", IEEE Transactions on CAD of Integrated Circuits and Systems, vo.20, no.3, pp. 369-380, March 2001.
4. N.Kranitis, G.Xenoulis, A.Paschalis, D.Gizopoulos, Y.Zorian, "Low-Cost Software-Based Self-Testing of RISC Processor Cores", in Proc. of the IEEE DATE 2003.
5. H.Al-Assad, B.T.Murray, J.P.Hayes, "Online BIST for Embedded Systems", in IEEE Design & Test of Computers, vol.15, no.4, Oct.-Dec. 1998, pp.17-24
6. M.Nicolaidis, Y.Zorian, "On-line Testing for VLSI - A Compendium of approaches", in Journal of Electronic Testing: Theory and Applications, Vol. 12, No. 1-2, 1998, pp 7-20
7. N. Oh, E.J.McCluskey, "Error Detection by Selective Procedure Call Duplication for Low Energy Consumption", in IEEE Trans. on Reliability, Vol. 51, No. 4 December 2002 pp.392-402
8. J.Hennessy, D.Patterson, "Computer Architecture A Quantitative Approach", MKP, 1996
9. Intel Corporation, Mobile Power Guidelines 2000, Dec 11, 1998
10. Plasma CPU Model. http://www.opencores.org/projects/mips
11. J. Phil, E.Sand, Arithmetic Module Generator for High Performance VLSI Designs. http://www.fysel.ntnu.no/modgen/