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Volumn , Issue , 2004, Pages 193-198

Time-interleaved analog-to-digital converters for digital communications

Author keywords

Analog circuits; Calibration; Communication systems; Digital signal processing

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; CALIBRATION; CMOS INTEGRATED CIRCUITS; COMMUNICATION SYSTEMS; DIGITAL SIGNAL PROCESSING; EQUALIZERS; ERROR DETECTION; GAIN CONTROL; MATHEMATICAL MODELS; SIGNAL TO NOISE RATIO;

EID: 11144254605     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (9)

References (16)
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  • 3
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    • Analysis of mismatch effects among A/D converters in a time-interleaved waveform digitizers
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    • (1991) IEEE Trans. Instrum. and Meas. , vol.40 , Issue.5 , pp. 831-835
    • Petraglia, A.1    Mitra, S.K.2
  • 4
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    • An analog background calibration technique for time-interleaved analog-to-digital converters
    • K. C. Dyer, D. Fu, S. H. Lewis, & P. J. Hurst, An analog background calibration technique for time-interleaved analog-to-digital converters, IEEE Journal of Solid-State Circuits, 33(12), 1998, 1912-1919.
    • (1998) IEEE Journal of Solid-state Circuits , vol.33 , Issue.12 , pp. 1912-1919
    • Dyer, K.C.1    Fu, D.2    Lewis, S.H.3    Hurst, P.J.4
  • 5
    • 0032313025 scopus 로고    scopus 로고
    • A digital background calibration technique for time-interleaved analog-to-digital converters
    • D. Fu, K. C. Dyer, S. H. Lewis, & P. J. Hurst, A digital background calibration technique for time-interleaved analog-to-digital converters, IEEE Journal of Solid-State Circuits, 33(12), 1998, 1904-1911.
    • (1998) IEEE Journal of Solid-state Circuits , vol.33 , Issue.12 , pp. 1904-1911
    • Fu, D.1    Dyer, K.C.2    Lewis, S.H.3    Hurst, P.J.4
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    • S. M. Jamal, D. Fu, S. H. Lewis, & P. J. Hurst, A 10-bit 120 Msample/s time-interleaved analog-to-digital converter with digital background calibration, IEEE Journal of Solid-State Circuits, 37(12), 2002, 1618-1627.
    • (2002) IEEE Journal of Solid-state Circuits , vol.37 , Issue.12 , pp. 1618-1627
    • Jamal, S.M.1    Fu, D.2    Lewis, S.H.3    Hurst, P.J.4
  • 8
    • 0034225769 scopus 로고    scopus 로고
    • A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs
    • H. Jin & E. K. F. Lee, A digital-background calibration technique for minimizing timing-error effects in time-interleaved ADCs, IEEE Transactions on Circuits and Systems II, 47(7), 2000, 603-613.
    • (2000) IEEE Transactions on Circuits and Systems II , vol.47 , Issue.7 , pp. 603-613
    • Jin, H.1    Lee, E.K.F.2
  • 14
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  • 15
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    • Performance and implementation of adaptive partial response maximum likelihood detection
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  • 16
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    • Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter
    • S. M. Jamal, D. Fu, M. P. Singh, P. J. Hurst & S. H. Lewis, Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter, IEEE Transactions on Circuit and System I, 51(1), 2004, 130-139.
    • (2004) IEEE Transactions on Circuit and System I , vol.51 , Issue.1 , pp. 130-139
    • Jamal, S.M.1    Fu, D.2    Singh, M.P.3    Hurst, P.J.4    Lewis, S.H.5


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.