Inegrated floorplanning with buffer/channel insertion for bus-based microprocessor designs

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2002, Pages 56-61

  Rafiq, Faran ^a   Chrzanowska Jeske, Malgorzata ^a   Yang, Hannah Honghua ^a   Sherwani, Naveed ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Floorplanning; Interconnect estimation; Routability

Indexed keywords

ALGORITHMS; BENCHMARKING; DESIGN FOR TESTABILITY; ROUTERS;

MICROPROCESSOR DESIGNS;

MICROPROCESSOR CHIPS;

EID: 0036374273     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

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9. A new algorithm for floorplan design
10. An O-tree representation of non-slicing floorplan and its application
11. Combing evolution strategies with lagrangian relaxation for constructing non-slicing VLSI floorplans with soft modules