Faster and more accurate wiring evaluation in interconnect-centric floorplanning

Proceedings of the IEEE Great Lakes Symposium on VLSI

Volumn , Issue , 2001, Pages 62-67

  Chen, H M ^a   Wong, D F ^a   Mak, W K ^a   Yang, H H ^a  

^a University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; PROGRAM PROCESSORS; RESPONSE TIME (COMPUTER SYSTEMS); ROUTERS; VLSI CIRCUITS;

INTERCONNECT-CENTRIC FLOORPLANNING;

INTEGRATED CIRCUIT LAYOUT;

EID: 0035020693     PISSN: 10661395     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/368122.368798     Document Type: Conference Paper

References (14)