Total dose effects on double gate fully depleted SOI MOSFETs

IEEE Transactions on Nuclear Science

Volumn 51, Issue 6 II, 2004, Pages 3767-3772

  Jun, Bongim ^a   Xiong, Hao D ^a   Sternberg, Andrew L ^a   Cirba, Claude R ^a   Chen, Dakai ^a   Schrimpf, Ronald D ^a   Fleetwood, Daniel M ^a   Schwank, James R ^b   Cristoloveanu, Sorin ^c  

^a VANDERBILT UNIVERSITY   (United States)

^b SANDIA NATIONAL LABORATORIES   (United States)

^c Grenoble INP Phelma   (France)

Author keywords

Charge coupling; Double gate; Fully depleted (FD) silicon on insulator (SOI) transistors; Total dose effects

Indexed keywords

CAPACITANCE; FUNCTIONS; GATES (TRANSISTOR); MOSFET DEVICES; SILICON ON INSULATOR TECHNOLOGY; THRESHOLD VOLTAGE; TRANSCONDUCTANCE;

BURIED OXIDE LAYER (BOX); CHARGE COUPLING; DOUBLE GATES; FULLY-DEPLETED (FD); TOTAL DOSE EFFECTS;

DOSIMETRY;

EID: 11044235408     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.839256     Document Type: Conference Paper

References (18)

1. J. P. Colinge, Silicon-On-Insulator Technology: Materials to VLSI. Dordrecht, Germany: Kluwer, 1991.
2. S. Cristoloveanu and S. S. Li, Electrical Characterization of Silicon-On-Insulator Materials and Devices. Dordrecht, Germany: Kluwer, 1995.
3. F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, "Double-gate silicon-on-insulator transistor with volume inversion: A new device with greatly enhanced performance," IEEE Electron Device. Lett., vol. EDL-8, pp. 410-412, Sept. 1987.
4. T. Ernst, S. Cristoloveanu, G. Ghibaudo, T. Ouisse, S. Horoguchi, Y. Ono, Y. Takahashi, and K. Murase, "Ultimately thin double-gate SOI MOSFETs," IEEE Trans. Electron Devices, vol. 50, pp. 830-838, Mar. 2003.
5. Y. Omura, S. Horiguchi, M. Tabe, and K. Kishi, "Quantum-mechnical effects on the threshold voltage of ultrathin-SOI nMOSFETs," IEEE Electron Device Lett., vol. 14, pp. 569-571, Dec. 1993.
6. S. Cristoloveanu, T. Ernst, D. Munteanu, and T. Ouisse, "Int. J. of high speed electronics and systems," in Frontiers in Electronics: From Materials to Systems, Y. S. Park, S. Luryi, M. S. Shur, J. M. Xu, and A. Zaslavsky, Eds, Singapore: World Scientific, 2000, vol. 10, pp. 217-217.
7. C. Cirba, S. Cristoloveanu, R. D. Schrimpf, L. C. Feldman, D. M. Fleetwood, and K. F. Galloway, "Total dose radiation hardness of double-gate ultra-thin SOI MOSFETs," in Proc. 11th Int. Symp. Silicon on Insulator Technology and Devices, 2003.
8. F. Allibert, M. Vinet, J. Lolivier, S. Deleonibus, and S. Cristoloveanu, "Characterization of ultra-thin SOI films for double-gate MOSFETs," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 187-187.
9. S. T. Liu, "Effect of total dose radiation on FET's fabricated in UNIBOND SOI material," in Proc. IEEE Int. SOI Conf., Oct. 1996, pp. 94-95.
10. R. K. Lawrence, B. J. Mrstik, H. L. Hughes, and P. J. McMarr, "Dependence of radiation induced buried oxide charge on silicon-on insulator fabrication technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2639-2645, Dec. 1996.
11. M. G. Ancona and H. F. Tiersten, "Macroscopic review of Si inversion layers," Phys. Rev. B., vol. 35, pp. 7959-7965, 1987.
12. M. G. Ancona and G. J. Iafrate, "Quantum correction to the equation of state of an electron gas in a semiconductor," Phys. Rev. B., vol. 39, pp. 9536-9540, 1989.
13. E. Lyumkis, R. Mickevicious, O. Penzin, B. Polsky, K. Elsaved, A. Wettstein, and W. Fichner, "Density gradient transport model for the simulations of ultrathin, untrashort SOI under nonequilibrium conditions," in Proc. IEEE Int. SOI Conf., Oct. 2002, pp. 143-144.
14. H. K. Kim and J. G. Fossum, "Threshold voltage of thin-film silicon-on-insulator (SOI) MOSFETs," IEEE Trans. Electron Devices, vol. 30, pp. 1244-1251, 1983.
15. G. Ghibaudo, "New method for the extraction of MOSFET parameters," Electron. Lett., vol. 24, pp. 543-545, Sept. 1988.
16. 2 structures by lamp annealing of oxygen implanted Si," in Proc. IEEE SOS/SOI Workshop, Oct. 1986.
17. B. Yu, L. Chang, S. Ahmed, H. Wang, S. Bell, C. Yang, C. Tabery, C. Ho, Q. Xiang, T. King, J. Bokor, C. Hu, M. Lin, and D. Kyser, "FinFET scaling to 10 nm gate length," in IEDM Electron Device Meeting, Dec. 2002, pp. 251-254.
18. A. Burenkov and J. Lorenz, "Corner effect in double and triple gate Fin-FETs," in Proc. 33rd ESSDERC Conf., Sept. 16-18, 2003.