메뉴 건너뛰기




Volumn 51, Issue 6 II, 2004, Pages 3510-3518

Software detection mechanisms providing full coverage against single bit-flip faults

Author keywords

Control flow checking; Data computing block (DCB); Exhaustive fault injection experiments; Signature monitoring technique; Software error detection

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SOFTWARE; CONTROL SYSTEMS; DATA ACQUISITION; MICROPROCESSOR CHIPS; PROGRAM PROCESSORS; SEMICONDUCTOR MATERIALS;

EID: 11044229324     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2004.839110     Document Type: Conference Paper
Times cited : (61)

References (24)
  • 3
    • 0000431078 scopus 로고
    • Low cost concurrent error detection in a VLIW architecture using replicated instructions
    • J. G. Holm and P. Banerjee, "Low cost concurrent error detection in a VLIW architecture using replicated instructions," in Proc. Int. Conf. Parallel Processing, 1992, pp. 192-195.
    • (1992) Proc. Int. Conf. Parallel Processing , pp. 192-195
    • Holm, J.G.1    Banerjee, P.2
  • 4
    • 0036507790 scopus 로고    scopus 로고
    • Error detection by duplicated instructions in super-scalar processors
    • Mar.
    • N. Oh, P. Shirvani, and E. J. McCluskey, "Error detection by duplicated instructions in super-scalar processors," IEEE Trans. Rel., vol. 51, pp. 63-75, Mar. 2002.
    • (2002) IEEE Trans. Rel. , vol.51 , pp. 63-75
    • Oh, N.1    Shirvani, P.2    McCluskey, E.J.3
  • 5
    • 0008534424 scopus 로고
    • Error detecting and correcting binary code for arithmetic operation
    • Sept.
    • D. T. Brown, "Error detecting and correcting binary code for arithmetic operation," Trans. Electronic Computers, vol. 9, pp. 333-337, Sept. 1960.
    • (1960) Trans. Electronic Computers , vol.9 , pp. 333-337
    • Brown, D.T.1
  • 6
    • 0020152817 scopus 로고
    • Concurrent error detection in ALU's by recomputing with shifted operands
    • July
    • H. J. Patel and L. Y. Fung, "Concurrent error detection in ALU's by recomputing with shifted operands," IEEE Trans. Comput., vol. 31, pp. 589-595, July 1982.
    • (1982) IEEE Trans. Comput. , vol.31 , pp. 589-595
    • Patel, H.J.1    Fung, L.Y.2
  • 7
    • 0036472442 scopus 로고    scopus 로고
    • 4 I: Error detection by diverse data and duplicated instruction
    • Feb.
    • 4 I: Error detection by diverse data and duplicated instruction," IEEE Trans. Comput., vol. 51, pp. 180-199, Feb. 2002.
    • (2002) IEEE Trans. Comput. , vol.51 , pp. 180-199
    • Oh, N.1    Mitra, S.2    McCluskey, E.J.3
  • 8
    • 0030691711 scopus 로고    scopus 로고
    • Data flow transformation to detect results which are corrupted by hardware faults
    • H. Engel, "Data flow transformation to detect results which are corrupted by hardware faults," in IEEE High Assurance Systems End. Workshop, 1997, pp. 279-285.
    • (1997) IEEE High Assurance Systems End. Workshop , pp. 279-285
    • Engel, H.1
  • 11
    • 0000347178 scopus 로고
    • An approach to concurrent control flow checking
    • Mar.
    • S. S. Yau and F. C. Chen, "An approach to concurrent control flow checking," IEEE Trans. Software Eng., vol. SE-6, pp. 126-137, Mar. 1980.
    • (1980) IEEE Trans. Software Eng. , vol.SE-6 , pp. 126-137
    • Yau, S.S.1    Chen, F.C.2
  • 12
    • 0036507891 scopus 로고    scopus 로고
    • Control-flow checking by software signatures
    • Mar.
    • N. Oh, P. P. Shirvani, and E. J. McCluskey, "Control-flow checking by software signatures," IEEE Trans. Rel., vol. 51, pp. 111-122, Mar. 2002.
    • (2002) IEEE Trans. Rel. , vol.51 , pp. 111-122
    • Oh, N.1    Shirvani, P.P.2    McCluskey, E.J.3
  • 14
  • 15
    • 0020302217 scopus 로고
    • Techniques for concurrent testing of VLSI processor operation
    • M. Namjoo, "Techniques for concurrent testing of VLSI processor operation," in Dig. Papers, IEEE Test Conf., 1982, pp. 461-468.
    • (1982) Dig. Papers, IEEE Test Conf. , pp. 461-468
    • Namjoo, M.1
  • 16
    • 0020914974 scopus 로고
    • On-line self-monitoring using signatured instruction streams
    • J. P. Shen and M. A. Schuette, "On-line self-monitoring using signatured instruction streams," in Int. Test Conf. Proc., 1982, pp. 275-282.
    • (1982) Int. Test Conf. Proc. , pp. 275-282
    • Shen, J.P.1    Schuette, M.A.2
  • 17
    • 0025416472 scopus 로고
    • Control-flow checking using watchdog assists and extended-precision checksums
    • Apr.
    • N. R. Saxena and E. J. McCluskey, "Control-flow checking using watchdog assists and extended-precision checksums," IEEE Trans. Comput., vol. 39, pp. 554-559, Apr. 1990.
    • (1990) IEEE Trans. Comput. , vol.39 , pp. 554-559
    • Saxena, N.R.1    McCluskey, E.J.2
  • 18
    • 0001599329 scopus 로고
    • On-line signature learning and checking
    • J. F. Schlichting and R. D. Schlichting, Eds:, vol. 6 in the series Dependable Computing and Fault-Tolerance, Springer-Verlag
    • H. Madeira and J. G. Silvia, "On-line signature learning and checking," in Dependable Computing for Critical Applications 2, J. F. Schlichting and R. D. Schlichting, Eds:, 1992, vol. 6 in the series Dependable Computing and Fault-Tolerance, Springer-Verlag, pp. 395-420.
    • (1992) Dependable Computing for Critical Applications 2 , pp. 395-420
    • Madeira, H.1    Silvia, J.G.2
  • 21
    • 33646063753 scopus 로고    scopus 로고
    • Reducing fault sensitivity of microprocessor-based system by modifying workload structure
    • Austin, TX, Nov. 2-4
    • D. Audet, S. Masson, and Y. Savaria, "Reducing fault sensitivity of microprocessor-based system by modifying workload structure," in IEEE Int. Symp. Defect Fault Tolerance VLSI Systems, Austin, TX, Nov. 2-4, 1998, pp. 241-249.
    • (1998) IEEE Int. Symp. Defect Fault Tolerance VLSI Systems , pp. 241-249
    • Audet, D.1    Masson, S.2    Savaria, Y.3
  • 22
    • 0034450666 scopus 로고    scopus 로고
    • Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code emulating Upsets) injection
    • Dec.
    • R. Velazco, S. Rezgui, and R. Ecoffet, "Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code emulating Upsets) injection," IEEE Trans. Nucl. Sci., vol. 47, pp. 2405-2411, Dec. 2000.
    • (2000) IEEE Trans. Nucl. Sci. , vol.47 , pp. 2405-2411
    • Velazco, R.1    Rezgui, S.2    Ecoffet, R.3
  • 23
    • 0036952552 scopus 로고    scopus 로고
    • Validation of an SEU simulation technique for a complex processor: PowerPC7400
    • Dec.
    • S. Rezgui, G. M. Swift, R. Velazco, and F. Farmanesh, "Validation of an SEU simulation technique for a complex processor: PowerPC7400," IEEE Trans. Nucl. Sci., vol. 49, pp. 3156-3162, Dec. 2002.
    • (2002) IEEE Trans. Nucl. Sci. , vol.49 , pp. 3156-3162
    • Rezgui, S.1    Swift, G.M.2    Velazco, R.3    Farmanesh, F.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.