Estimating Error Rates in Processor-Based Architectures

IEEE Transactions on Nuclear Science

Volumn 48, Issue 5, 2001, Pages 1680-1687

  Rezgui, Sana ^a   Velazco, Raoul ^b   Ecoffet, Robert ^b   Rodriguez, Santiago ^c   Mingo, Jose Ramon ^c  

^a TIMA LABORATORY   (France)

^b French Space Agency CNES31401   (France)

^c Spanish Research Agency ^*  (Spain)

Author keywords

Fault injection; ground testing

Indexed keywords

EID: 85008053865     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.960357     Document Type: Article

References (9)

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7. R. Velazco, S. Rezgui, and R. Ecoffet, “Predicting error rate for microprocessor-based digital architectures through C.E.U. (Code Emulating Upsets) injection,” IEEE Trans. Nucl. Sci., vol. 47, Dec. 2000.
8. R. Velazco, P. Cheynet, A. Bofill, and R. Ecoffet, “THESIC: A testbed suitable for the qualification of integrated circuits devoted to operate in harsh environment,” in Proc. IEEE Eur. Test Workshop (ETW'98), Sitges, Spain, May 1998, pp. 89-90.
9. R. Velazco and S. Rezgui, “Error rate estimation process for digital architectures exposed to radiation,” patent pending, Jan. 16, 2001.