CMOS layout and bias optimization for RF IC design applications

IEEE MTT-S International Microwave Symposium Digest

Volumn 2, Issue , 1997, Pages 945-948

  Kim, Cheon Soo ^a   Yu, Hyun Kyu ^a   Cho, Hanjin ^a   Lee, Seonghearn ^a   Nam, Kee Soo ^a  

^a Electronics and Telecommunications Research Institute (ETRI)   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; NATURAL FREQUENCIES; SILICON WAFERS; SPURIOUS SIGNAL NOISE;

POLYSILICON GATE;

MOSFET DEVICES;

EID: 0030648274     PISSN: 0149645X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)