메뉴 건너뛰기




Volumn 2003-January, Issue , 2003, Pages 635-639

Silicon virtual prototyping: The new cockpit for nanometer chip design [SoC]

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; DESIGN; ITERATIVE METHODS; MICROPROCESSOR CHIPS; MOBILE TELECOMMUNICATION SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; SILICON; SYSTEM-ON-CHIP; VIRTUAL PROTOTYPING;

EID: 0742275741     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2003.1195101     Document Type: Conference Paper
Times cited : (5)

References (8)
  • 1
    • 84954450367 scopus 로고    scopus 로고
    • Hierarchical design methodology for multi-million gates ASICs
    • W.J. Dai, "Hierarchical design methodology for multi-million gates ASICs," DesignCon 2001.
    • DesignCon 2001
    • Dai, W.J.1
  • 3
    • 0003945440 scopus 로고    scopus 로고
    • Kluwer Academic Publishers
    • rd Ed., Kluwer Academic Publishers, 1999.
    • (1999) rd Ed.
    • Sherwani, N.1
  • 8
    • 84954411118 scopus 로고
    • Pin assignment with global routing for general cell design
    • J. Cong, "Pin assignment with global routing for general cell design", IEEE Trans. Computer-Aided Design, vol. 28, no. 20, pp. 1882-1884, 1992.
    • (1992) IEEE Trans. Computer-Aided Design , vol.28 , Issue.20 , pp. 1882-1884
    • Cong, J.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.