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Volumn 12, Issue 6, 2003, Pages 863-872

Planar CMOS compatible process for the fabrication of buried microchannels in silicon, using porous-silicon technology

Author keywords

Buried microchannels; Microfluidic sensor; Porous silicon technology

Indexed keywords

ELECTROLYTIC POLISHING; INTEGRATED CIRCUIT MANUFACTURE; LITHOGRAPHY; OPTIMIZATION; POROUS SILICON; SEMICONDUCTING SILICON;

EID: 0742269314     PISSN: 10577157     EISSN: None     Source Type: Journal    
DOI: 10.1109/JMEMS.2003.820270     Document Type: Article
Times cited : (41)

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