Wafer thinning for monolithic 3D integration

Materials Research Society Symposium - Proceedings

Volumn 766, Issue , 2003, Pages 21-26

  Jindal, A ^a   Lu, J Q ^a   Kwon, Y ^a   Rajagopalan, G ^a   McMahon, J J ^a   Zeng, A Y ^a   Flesher, H K ^b   Cale, T S ^a   Gutmann, R J ^a  

^a RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^b Aptek Industries Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; COPPER; ETCHING; GRINDING (MACHINING); INTERFACES (MATERIALS); POLISHING; SILICON WAFERS; SUBSTRATES;

DAMAGE FREE INTERCONNECT STRUCTURES; EDGE CHIPPING; THREE STEP BASELINE THINNING PROCESS; WAFER BREAKAGE; WAFER THINNING;

MONOLITHIC INTEGRATED CIRCUITS;

EID: 0348199189     PISSN: 02729172     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1557/proc-766-e5.7     Document Type: Conference Paper

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