A 33mW 8Gb/s CMOS clock multiplier and CDR for highly integrated I/Os

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 2003, Pages 77-80

  Ng, Hiok Tiaq ^a   Lee, M J Edward ^a   Farjad Rad, Ramin ^a   Senthinathan, Ramesh ^a   Dally, William J ^b   Nguyen, Anhtuyet ^a   Rathi, Rohit ^a   Greer, Trey ^a   Poulton, John ^a   Edmondson, John ^a   Tran, James ^a  

^a Velio Communications Inc   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; CAPACITORS; INTERFERENCE SUPPRESSION; JITTER; MULTIPLYING CIRCUITS; OSCILLATORS (ELECTRONIC); RESISTORS; VOLTAGE REGULATORS;

CLOCK AND DATA RECOVERY CIRCUIT; CLOCK MULTIPLIER; INJECTION LOCKING; JITTER SUPPRESSION; PHASE INTERPOLATION; SLAVE INJECTION LOCKED OSCILLATOR;

CMOS INTEGRATED CIRCUITS;

EID: 0242527308     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

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