Equalization and clock recovery for a 2.5 - 10Gb/s 2-PAM/4-PAM backplane transceiver cell

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Zerbe, J ^a   Werner, C ^a   Stojanovic, V ^a   Chen, F ^a   Wei, J ^a   Tsang, G ^a   Kim, D ^a   Stonecypher, W ^a   Ho, A ^a   Thrush, T ^a   Kollipara, R ^a   Yeh, G J ^a   Horowitz, M ^b   Donnelly, K ^a  

^a Rambus   (United States)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; BIT ERROR RATE; COMPUTER SIMULATION; EQUALIZERS; FIR FILTERS; INSERTION LOSSES; JITTER; TIMING CIRCUITS; TRANSMITTERS;

CLOCK RECOVERY CIRCUIT; DECISION FEEDBACK-BASED RECEIVE EQUALIZATION;

TRANSCEIVERS;

EID: 0037969368     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (7)

1. M.M. Green, et al., "OC-192 Transmitter in Standard 0.18 μm CMOS," ISSCC Digest of Technical Papers, pp. 248-249, 2002.
2. J. Zerbe, et al., "A 2Gb/s/pin 4-PAM Parallel Bus Interface with Crosstalk Cancellation, Equalization, and Integrating Receivers," ISSCC Digest of Technical Papers, pp. 66-67, 2001.
3. R. Farjad-Rad, et al., IEEE J. Solid-State Circuits, vol. 35, pp. 757-764, May 2000.
4. C.-K. Yang, et al., "A Serial-Link Transceiver Based on 8-GSamples/s A/D and D/A Converters in 0.25μm CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1684-1692, November 2001.
5. A. Fiedler, et al., "A 1.0625Gbps Transceiver with 2x-Oversampling and Transmit Signal Pre-emphasis," ISSCC Digest of Technical Papers, pp. 238-239, 1997.
6. K. Chang, et al., "A 0.4-4Gbb/s CMOS Quad Transceiver Cell Using On-Chip Regulated Dual-Loop PLLs," 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 88-91.
7. S. Sidiropoulos, M. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683-1692, November 1997.