Ratio based hot-carrier degradation modeling for aged timing simulation of millions of transistors digital circuits

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 1998, Pages 93-96

  Yonezawa, Hirokazu ^a   Fang, Jingkun ^a   Kawakami, Yoshiyuki ^a   Iwanishi, Nobufusa ^a   Wu, Lifeng ^a   Chen, Alvin I Hsien ^a   Koike, Norio ^a   Chen, Ping ^a   Yeh, Chune Sin ^a   Liu, Zhihong ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL INTEGRATED CIRCUITS; GATES (TRANSISTOR); HOT CARRIERS; MATHEMATICAL MODELS;

TRANSISTOR DIGITAL CIRCUITS;

CMOS INTEGRATED CIRCUITS;

EID: 0032276824     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)