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Volumn 15, Issue 5, 1996, Pages 453-464

Computer-aided redesign of VLSI circuits for hot-carrier reliability

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DEGRADATION; FAILURE ANALYSIS; HOT CARRIERS; INTEGRATED CIRCUIT LAYOUT; MOSFET DEVICES; RELIABILITY; SEMICONDUCTOR DEVICE MODELS; VLSI CIRCUITS;

EID: 0030147857     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.506133     Document Type: Article
Times cited : (6)

References (36)
  • 1
    • 0027591398 scopus 로고
    • P. Yang J.-H. Chern Design for reliability: The major challenge for VLSI Proc. IEEE 81 730 744 May 1993 5 5770 220904
    • (1993) , vol.81 , pp. 730-744
    • Yang, P.1    Chern, J.-H.2
  • 3
    • 0024072045 scopus 로고
    • W. Weber Dynamic stress experiments for understanding hot-carrier degradation phenomena IEEE Trans. Electron Devices 35 1476 1486 Sept. 1988 16 153 2580
    • (1988) , vol.35 , pp. 1476-1486
    • Weber, W.1
  • 4
    • 84945713471 scopus 로고
    • C. Hu S. Tam F. C. Hsu P. K. Ko T. Y. Chan K. W. Terrill Hot-Electron-induced MOSFET degradation—Model, monitor, and improvement IEEE Trans. Electron Devices ED-32 375 384 Feb. 1985
    • (1985) , vol.ED-32 , pp. 375-384
    • Hu, C.1    Tam, S.2    Hsu, F.C.3    Ko, P.K.4    Chan, T.Y.5    Terrill, K.W.6
  • 5
    • 0028516240 scopus 로고
    • P. C. Li G. I. Stamoulis I. N. Hajj A probabilistic timing approach to hot-carrier effect estimation IEEE Trans. Computer-Aided Design 13 1223 1234 Oct. 1994 43 7650 317465
    • (1994) , vol.13 , pp. 1223-1234
    • Li, P.C.1    Stamoulis, G.I.2    Hajj, I.N.3
  • 6
    • 85176674945 scopus 로고
    • M. G. Xakellis F. N. Najm Statistical estimation of the switching activity in digital circuits Proc. ACM/IEEE Design Automation Conf. 728 733 June 1994
    • (1994) , pp. 728-733
    • Xakellis, M.G.1    Najm, F.N.2
  • 7
    • 0027224407 scopus 로고
    • B. S. Doyle K. R. Mistry The characterization of hot-carrier damage in $p$-channel transistors IEEE Trans. Electron Devices 40 152 156 1993 16 6383 249438
    • (1993) , vol.40 , pp. 152-156
    • Doyle, B.S.1    Mistry, K.R.2
  • 8
    • 85176686058 scopus 로고
    • W. Sun E. Rosenbaum S. M. Kang Fast timing simulation for submicron hot-carrier degradation Proc. Int. Rel. Phys. Symp. 65 71 1994 3893 11322 513656
    • (1994) , pp. 65-71
    • Sun, W.1    Rosenbaum, E.2    Kang, S.M.3
  • 9
    • 0028742140 scopus 로고
    • R. Kao M. Horowitz Timing analysis for piecewise linear Rsim IEEE Trans. Computer-Aided Design 13 1498 1512 Dec. 1994 43 7831 331407
    • (1994) , vol.13 , pp. 1498-1512
    • Kao, R.1    Horowitz, M.2
  • 10
    • 0028756124 scopus 로고
    • J. Qian S. Pullela L. Pillage Modeling the effective capacitance for the $RC$ interconnect of CMOS gates IEEE Trans. Computer-Aided Design 13 1526 1535 Dec. 1994 43 7831 331409
    • (1994) , vol.13 , pp. 1526-1535
    • Qian, J.1    Pullela, S.2    Pillage, L.3
  • 11
    • 0020778211 scopus 로고
    • J. Rubenstein P. Penfield M. Horowitz Signal delay in $RC$ tree networks IEEE Trans. Computer-Aided Design CAD-2 202 211 July 1983
    • (1983) , vol.CAD-2 , pp. 202-211
    • Rubenstein, J.1    Penfield, P.2    Horowitz, M.3
  • 12
    • 85176670498 scopus 로고
    • Addison Wesley MA, Reading
    • J. P. Uyemura Fundamentals of MOS Digital Integrated Circuits 1988 Addison Wesley MA, Reading
    • (1988)
    • Uyemura, J.P.1
  • 13
    • 0021378416 scopus 로고
    • F. Hsu S. Tam Relationship between MOSFET degradation and hot-electron-induced interface-state generation IEEE Electron Device Lett. EDL-5 50 52 Feb. 1984
    • (1984) , vol.EDL-5 , pp. 50-52
    • Hsu, F.1    Tam, S.2
  • 14
    • 0020155309 scopus 로고
    • C. Lombardi P. Olivo B. Ricco E. Sangiorgi M. Vanzi Hot electrons in MOS transistors: Lateral distribution of the trapped oxide charge IEEE Electron Device Lett. EDL-3 215 217 July 1982
    • (1982) , vol.EDL-3 , pp. 215-217
    • Lombardi, C.1    Olivo, P.2    Ricco, B.3    Sangiorgi, E.4    Vanzi, M.5
  • 15
    • 85176678773 scopus 로고
    • Y. Leblebici S. M. Kang A one-dimensional MOSFET model for simulation of hot-carrier induced device and circuit degradation Proc. IEEE Int. Symp. Circuits Syst. 109 112 May 1990 143 3356 111929
    • (1990) , pp. 109-112
    • Leblebici, Y.1    Kang, S.M.2
  • 16
    • 0023315137 scopus 로고
    • N. Hedenstierna K. O. Jeppson CMOS circuit speed and buffer optimization IEEE Trans. Computer-Aided Design CAD-6 270 281 Mar. 1987
    • (1987) , vol.CAD-6 , pp. 270-281
    • Hedenstierna, N.1    Jeppson, K.O.2
  • 17
    • 0024719363 scopus 로고
    • H. J. Park K. Lee C. K. Kim A new CMOS NAND logic circuit for reducing hot-carrier problems IEEE J. Solid-State Circuits 24 1041 1047 Aug. 1989 4 1419 34090
    • (1989) , vol.24 , pp. 1041-1047
    • Park, H.J.1    Lee, K.2    Kim, C.K.3
  • 18
    • 0022671552 scopus 로고
    • T. Sakurai Hot-carrier generation in submicrometer VLSI environment IEEE J. Solid-State Circuits SC-21 187 192 Feb. 1986
    • (1986) , vol.SC-21 , pp. 187-192
    • Sakurai, T.1
  • 19
    • 85176668377 scopus 로고
    • L. Bruni G. Buonanno D. Sciuto Transistor stuck-at and delay faults detection in static and dynamic CMOS combinational gates Proc. IEEE Int. Symp. Circuits Syst. 431 434 May 1992 640 5935 229921
    • (1992) , pp. 431-434
    • Bruni, L.1    Buonanno, G.2    Sciuto, D.3
  • 20
    • 85176692220 scopus 로고    scopus 로고
  • 21
    • 85176695610 scopus 로고
    • B. S. Carlson C. Y. R. Chen Performance enhancement of CMOS, VLSI circuits by transistor reordering Proc. ACM/IEEE 30th Design Automation Conf. 361 366 June 1993
    • (1993) , pp. 361-366
    • Carlson, B.S.1    Chen, C.Y.R.2
  • 22
    • 85176683957 scopus 로고
    • CA, Napa Valley
    • S. C. Prasad K. Roy Circuit optimization for minimization of power consumption under delay constraint Proc. Int. Wkshp. Low Power Des. 15 20 Apr. 1994 CA, Napa Valley
    • (1994) , pp. 15-20
    • Prasad, S.C.1    Roy, K.2
  • 23
    • 85176677059 scopus 로고
    • CA, Napa Valley
    • C. H. Tan J. Allen Minimizing of power in VLSI circuits using transistor sizing, input ordering, and statistical power estimation Proc. Int. Wkshp. Low Power Des. 75 80 Apr. 1994 CA, Napa Valley
    • (1994) , pp. 75-80
    • Tan, C.H.1    Allen, J.2
  • 24
    • 85176667932 scopus 로고
    • CA, Dana Point
    • A. L. Glebov D. Blaauw L. G. Jones Transistor reordering for low power CMOS gates using an SP-BDD representation Proc. Int. Symp. Low Power Des. 161 166 Apr. 1995 CA, Dana Point
    • (1995) , pp. 161-166
    • Glebov, A.L.1    Blaauw, D.2    Jones, L.G.3
  • 25
    • 0005032807 scopus 로고
    • T. I. Kirkpatrick N. R. Clark PERT as an aid to logic design IBM J. Res. Develop. 10 135 141 Mar. 1966
    • (1966) , vol.10 , pp. 135-141
    • Kirkpatrick, T.I.1    Clark, N.R.2
  • 26
    • 85176693037 scopus 로고
    • P. McGeer R. K. Brayton Efficient algorithms for computing the longest viable path in a combinational network Proc. ACM/IEEE Design Automation Conf. 561 567 July 1989
    • (1989) , pp. 561-567
    • McGeer, P.1    Brayton, R.K.2
  • 27
    • 85176687742 scopus 로고
    • Y. C. Ju R. A. Saleh Incremental techniques for the identification of statically sensitizable critical paths Proc. ACM/IEEE Design Automation Conf. 541 546 June 1991
    • (1991) , pp. 541-546
    • Ju, Y.C.1    Saleh, R.A.2
  • 28
    • 85176679405 scopus 로고
    • CA, Santa Clara
    • J. P. Fishburn A. E. Dunlop TILOS—A posynomial programming approach to transistor sizing Proc. IEEE Int. Conf. Computer-Aided Design 326 328 Nov. 1985 CA, Santa Clara
    • (1985) , pp. 326-328
    • Fishburn, J.P.1    Dunlop, A.E.2
  • 30
    • 0027701389 scopus 로고
    • S. S. Sapatnekar V. B. Rao P. M. Vaidya S. M. Kang An exact solution to the transistor sizing problem for CMOS circuits using convex optimization IEEE Trans. Computer-Aided Design 12 1621 1634 Nov. 1993 43 6352 248073
    • (1993) , vol.12 , pp. 1621-1634
    • Sapatnekar, S.S.1    Rao, V.B.2    Vaidya, P.M.3    Kang, S.M.4
  • 31
    • 85176693732 scopus 로고
    • S. Lin M. Marek-Sadowska E. S. Kuh Delay and area optimization is standard-cell design Proc. ACM/IEEE Design Automation Conf. 349 352 June 1990 790 3382 114880
    • (1990) , pp. 349-352
    • Lin, S.1    Marek-Sadowska, M.2    Kuh, E.S.3
  • 32
    • 0029264123 scopus 로고
    • W. Chuang S. S. Sapatnekar I. N. Hajj Timing and area optimization for standard-cell VLSI circuit designs IEEE Trans. Computer-Aided Design 14 308 320 Mar. 1995 43 8364 365122
    • (1995) , vol.14 , pp. 308-320
    • Chuang, W.1    Sapatnekar, S.S.2    Hajj, I.N.3
  • 33
    • 85176685775 scopus 로고
    • Eindhoven Univ. Tech. The Netherlands, Eindhoven
    • M. R. C. M. Berkelaar Lp_Solve-Solve (Mixed Integer) Linear Programming Problem June 1992 Eindhoven Univ. Tech. The Netherlands, Eindhoven
    • (1992)
    • Berkelaar, M.R.C.M.1
  • 34
    • 85176678670 scopus 로고
    • F. Brglez H. Fujiwara A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran Proc. IEEE Int. Symp. Circuits Syst. 695 698 June 1985
    • (1985) , pp. 695-698
    • Brglez, F.1    Fujiwara, H.2
  • 36
    • 85176673698 scopus 로고
    • CA, San Francisco
    • S. Devadas S. Malik A survey of optimization techniques targeting low power VLSI circuits Proc. ACM/IEEE Des. Automat. Conf. 242 247 June 1995 CA, San Francisco
    • (1995) , pp. 242-247
    • Devadas, S.1    Malik, S.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.