Power fluctuation minimization during behavioral synthesis using ILP-based datapath scheduling

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2003, Pages 441-443

  Mohanty, Saraju P ^a   Ranganathan, N ^a   Chappidi, Sunil K ^a  

^a UNIVERSITY OF SOUTH FLORIDA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; RELIABILITY;

DYNAMIC FREQUENCY CLOCKING; POWER FLUCTUATION MINIMIZATION;

SCHEDULING;

EID: 0345413221     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

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