A low-noise fast-settling PLL with extended loop bandwidth enhancement by new adaptation technique

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 93-97

  Tang, Yiwu ^a   Zhou, Yingjie ^b   Bibyk, Steven ^a   Ismail, Mohammed ^a  

^a Ohio State University   (United States)

^b MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTIVE CONTROL SYSTEMS; BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FREQUENCY DIVIDING CIRCUITS; FREQUENCY SYNTHESIZERS; SPURIOUS SIGNAL NOISE;

CHANNEL SPACING; FREQUENCY DIVIDE RATIO;

PHASE LOCKED LOOPS;

EID: 0034781618     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2001.954679     Document Type: Article

References (6)

1. An adaptive PLL tuning system architecture combining high spectral purity and fast settling time
2. A low-noise fast-lock phase-locked loop with adaptive bandwidth control
3. Adaptive bandwidth DLLs and PLLs using regulated supply CMOS buffers
4. Adaptive phase locked loop for video signal sampling
5. A low-noise 900-MHz VCO in 0.6um CMOS