Analysis and minimization of phase noise of the digital hybrid PLL frequency synthesizer

IEEE Transactions on Consumer Electronics

Volumn 48, Issue 2, 2002, Pages 304-312

  Ryu, Heung Gyoon ^a   Lee, Hyun Seok ^a  

^a Chungbuk National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; MATHEMATICAL MODELS; PHASE LOCKED LOOPS; SPURIOUS SIGNAL NOISE; VARIABLE FREQUENCY OSCILLATORS;

PHASE NOISE;

FREQUENCY SYNTHESIZERS;

EID: 0036564108     PISSN: 00983063     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCE.2002.1010136     Document Type: Article

References (10)

1. A study of phase noise in CMOS oscillators
2. Noise in phase-locked loops
3. A low-noise phase-locked loop design by loop bandwidth optimization
4. Noise analysis of phase-locked loops
5. Noise properties of PLL systems
6. Analysis of jitter due to power-supply noise in phase-locked loops
7. A general theory of phase noise in electrical oscillators