8Gb/s differential simultaneous bidirectional link with 4mV 9ps waveform capture diagnostic capability

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Martin, Aaron ^a   Casper, Bryan ^a   Kennedy, Joe ^a   Jaussi, James ^a   Mooney, Randy ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BANDWIDTH; CAPACITORS; CMOS INTEGRATED CIRCUITS; DATA COMMUNICATION SYSTEMS; ELECTRIC IMPEDANCE; JITTER; SIGNAL RECEIVERS;

DELAY-LOCKED LOOP; EQUALIZED DRIVERS; LINEAR-FEEDBACK SHIFT REGISTER; OFFSET-CANCELING RECEIVERS; SOURCE-SYNCHRONOUS CLOCK CHANNELS; VARAIBLE OFFSET COMPARATOR;

TIMING CIRCUITS;

EID: 0037631100     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Haycock, M.; Mooney, R. "3.2GHz 6.4Gb/s per Wire Signaling in 0.18μm CMOS," ISSCC Digest of Technical Papers, pp 62 - 63, 2001.
2. Lee, M.-J.E.; Dally, W.; Chiang, P. "A 90mW 4Gb/s Equalized I/C Circuit with Input Offset Cancellation", ISSCC Digest of Technical Papers, pp. 252-253, 2000.
3. Sidiropoulos, S.; Horowitz, M., "A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range," ISSCC Digest of Technical Papers, pp. 332-333, 1997.
4. Tamura, H. et. al, "Partial Response Detection Technique for Driver Power Reduction in High Speed Memory-to-Processor Communications", ISSCC Digest of Technical Papers, pp 342-343, 1997.